View XC4VLX15_4462657.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

0
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
0 0
DS302 (v3.2) April 10, 2008
Product Specification
Virtex-4 FPGA Electrical Characteristics
Virtex(R)-4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance. Virtex-4 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -10 speed grade industrial device are the same as for a -10 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Virtex-4 FPGA Data Sheet is part of an overall set of documentation on the Virtex-4 family of FPGAs that is available on the Xilinx website: * * * * * * * * * Virtex-4 Family Overview, DS112 Virtex-4 FPGA User Guide, UG070 Virtex-4 Configuration Guide, UG071 XtremeDSP for Virtex-4 FPGAs User Guide, UG073 Virtex-4 Packaging and Pinout Specification, UG075 Virtex-4 PCB Designer's Guide, UG072 Virtex-4 RocketIOTM Multi-Gigabit Transceiver User Guide, UG076 Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide, UG074 PowerPC(R) 405 Processor Block Reference Guide, UG018
All specifications are subject to change without notice.
Virtex-4 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings Symbol
VCCINT VCCAUX VCCO VBATT VREF
Description
Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply Input reference voltage I/O input voltage relative to GND (all user and dedicated I/Os) I/O input voltage relative to GND (restricted to maximum of 100 user I/Os) (3,4) 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) -0.5 to 1.32 -0.5 to 3.0 -0.5 to 3.75 -0.5 to 4.05 -0.3 to 3.75 -0.75 to 4.05 -0.95 to 4.4
Units
V V V V V V
VIN
(Commercial Temperature)
-0.85 to 4.3
(Industrial Temperature)
V
-0.75 to VCCO +0.5 100 200
V mA mA
IIN
Current applied to an I/O pin, powered or unpowered Total current applied to all I/O pins, powered or unpowered
(c) 2004-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license therefrom. All other trademarks are the property of their respective owners.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 1
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 1: Absolute Maximum Ratings (Continued) Symbol Description
Voltage applied to 3-state 3.3V output (all user and dedicated I/Os) Voltage applied to 3-state 3.3V output (restricted to maximum of 100 user I/Os) (3,4) 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) AVCCAUXRX AVCCAUXTX AVCCAUXMGT VTRX VTTX TSTG TSOL TJ Receive auxiliary supply voltage relative to analog ground, GNDA (RocketIO pins) Transmit auxiliary supply voltage relative to analog ground, GNDA (RocketIO pins) Management auxiliary supply voltage relative to analog ground, GNDA (RocketIO pins) Terminal receive supply voltage relative to GND Terminal transmit supply voltage relative to GND Storage temperature (ambient) Maximum soldering Maximum junction temperature (2) -0.75 to 4.05 -0.95 to 4.4 VTS
(Commercial Temperature)
Units
V
-0.85 to 4.3
(Industrial Temperature)
V
-0.75 to VCCO +0.5 -0.5 to 1.32 -0.5 to 1.32 -0.5 to 3.0 -0.5 to 3.0 -0.5 to 1.65 -65 to 150 +220 +125
V V V V V V C C C
temperature (2)
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For soldering guidelines and thermal considerations, see the Virtex-4 Packaging and Pinout Specification on the Xilinx website. 3. When using more than 100 3.3V I/Os, refer to the Virtex-4 FPGA User Guide, Chapter 6, "3.3V I/O Design Guidelines." 4. For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal spec for no more than 20% of a data period. There are no bank restrictions.
Table 2: Recommended Operating Conditions Symbol
VCCINT
Description
Internal supply voltage relative to GND, TJ = 0 C to +85 C Internal supply voltage relative to GND, TJ = -40 C to +100 C Auxiliary supply voltage relative to GND, TJ = 0 C to +85 C Auxiliary supply voltage relative to GND, TJ = -40 C to +100 C Supply voltage relative to GND, TJ = 0 C to +85 C Supply voltage relative to GND, TJ = -40 C to +100 C 3.3V supply voltage relative to GND, TJ = 0 C to +85 C 3.3V supply voltage relative to GND, TJ = -40 C to +100 C Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Min
1.14 1.14 2.375 2.375 1.14 1.14 GND - 0.20 GND - 0.20 GND - 0.20 GND - 0.20
Max
1.26 1.26 2.625 2.625 3.45 3.45 3.45 3.45 VCCO + 0.2 VCCO + 0.2 10 10
Units
V V V V V V V V V V mA mA V V
VCCAUX VCCO(1,3,4,5)
VIN
2.5V and below supply voltage relative to GND, TJ = 0 C to +85 C 2.5V and below supply voltage relative to GND, TJ = -40 C to +100 C
IIN VBATT(2)
Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. Battery voltage relative to GND, TJ = 0 C to +85 C Battery voltage relative to GND, TJ = -40 C to +100 C
1.0 1.0
3.6 3.6
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 2
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 2: Recommended Operating Conditions (Continued) Symbol Description
Commercial Industrial AVCCAUXTX (6) Commercial Auxiliary transmit supply voltage relative to GNDA Industrial Commercial AVCCAUXMGT Auxiliary management supply voltage relative to GNDA Industrial VTRX (7) Commercial Terminal receive supply voltage relative to GND Industrial Commercial VTTX Terminal transmit supply voltage relative to GND Industrial 1.14 1.575 V 0.25 1.14 2.5 1.575 V V 2.375 0.25 2.625 2.5 V V 1.14 2.375 1.26 2.625 V V
Min
1.14 1.14 1.14
Max
1.26 1.26 1.26
Units
V V V
AVCCAUXRX (6) Auxiliary receive supply voltage relative to GNDA
Notes: 1. Configuration data is retained even if VCCO drops to 0V. 2. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX. 3. For 3.3V I/O operation, refer to the Virtex-4 FPGA User Guide. 4. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V 5. The configuration output supply voltage VCC_CONFIG is also known as VCCO_0 6. IMPORTANT! All unused RocketIO transceivers must be connected to power and GND. When using RocketIO transceivers, refer to the power filtering section of the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. Unused transceivers must be powered by an appropriate voltage level source. Passive filtering must meet the requirements discussed in the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. 7. Internal AC coupling is enabled.
Table 3: DC Characteristics Over Recommended Operating Conditions Symbol
VDRINT VDRI IREF IL CIN
Description
Data retention VCCINT voltage (below which configuration data might be lost) Data retention VCCAUX voltage (below which configuration data might be lost) VREF current per pin Input or output leakage current per pin (sample-tested) Input capacitance (sample-tested) Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.0V
Data Rate (Gb/s)
Min
0.9 2.0
Typ
Max
Units
V V
10 10 10 5 5 5 5 5 5 75 6.5 5.0 292 302 291 279 263 314 200 125 120 60 40 100 100 427 485 446 382 351
A A pF A A A A A A nA mA mA mA mA mA mA
IRPU(1)
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
IRPD(1) IBATT(1)
Pad pull-down (when selected) @ VIN = VCCO Battery supply current
I CCAUXRX (2)
4.25 Operating AVCCAUXRX supply current 3.125 1.25/2.5 1.25 Digital RX
432
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 3
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 3: DC Characteristics Over Recommended Operating Conditions (Continued) Symbol Description Data Rate (Gb/s)
6.5 5.0 I CCAUXTX (2) 4.25 Operating AVCCAUXTX supply current 3.125 2.5 1.25 I CCAUXMGT (2) I TTX (2) I TRX (2,3) Operating AVCCAUXMGT supply current Operating ITTX supply current when transmitter is AC coupled or VTTX = VTRX Operating ITRX supply current when receiver is AC coupled or VTTX = VTRX Temperature diode ideality factor Power dissipation of PowerPC 405 processor block Series resistance 165 157 151 3 100 12 1.02 0.45 2 307 298 295 5 210 24 mA mA mA mA mA mA n mW/MHz
Min
Typ
170 180 173
Max
339 355 330
Units
mA mA mA
n
PCPU
r
Notes: 1. Typical values are specified at nominal voltage, 25C. 2. ICC numbers given per tile with both MGT devices operating with default settings. 3. Varies with AC / DC coupling.
Table 4: Quiescent Supply Current
Symbol ICCINTQ Description Quiescent VCCINT supply current Device XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 Typ (1) 46 77 121 167 220 292 384 489 94 140 271 47 71 139 203 311 442 Max
Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6)
Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 4
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 4: Quiescent Supply Current (Continued)
Symbol ICCOQ Description Quiescent VCCO supply current Device XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 ICCAUXQ Quiescent VCCAUX supply current XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 ICCAUXRX
(4)
Typ (1) 1.25 1.25 1.25 1.5 1.5 1.75 2.5 2.5 1.25 1.25 1.5 1.25 1.25 1.25 1.5 1.75 2.5 31 36 43 74 83 95 133 150 62 70 91 31 35 69 80 98 143 25 35 50
Max
Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6) Note (6)
Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Quiescent AVCCAUXRX supply current
XC4VFX20 XC4VFX60 XC4VFX100
154 154 154
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 5
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 4: Quiescent Supply Current (Continued)
Symbol ICCAUXTX (4) Description Device XC4VFX20 XC4VFX60 XC4VFX100 ITTX (4,5) Typ (1) 10 15 20 1 1 1 1 1 1 1 1 1 Max 44 44 44 2 2 2 2 2 2 2 2 2 Units mA mA mA mA mA mA mA mA mA mA mA mA
Quiescent AVCCAUXTX supply current
Quiescent VTTX supply current
XC4VFX20 XC4VFX60 XC4VFX100
ITRX
(4,5)
Quiescent VTRX supply current
XC4VFX20 XC4VFX60 XC4VFX100
IAUXMGT
(4)
Quiescent VAUXMGT supply current
XC4VFX20 XC4VFX60 XC4VFX100
Notes:
1. 2. 3. 4. 5. 6. Typical values are specified at nominal voltage, 25C. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPower tool. Given for entire die. Powered and unconfigured. Unconnected (if channel is driven to voltage). Use the XPower Estimator (XPE) tool to calculate maximum static power for specific process, voltage, and temperature conditions.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 6
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Power-On Power Supply Requirements
Xilinx(R) FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. The power supplies can be turned on in any sequence, though the specifications shown in Table 5 are for the recommended power-on sequence of VCCINT, VCCAUX, VCCO. Xilinx does not specify the current for other power-on sequences. Table 5: Power-On Current for Virtex-4 Devices ICCINTMIN Device XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 Typ (1) 110 160 250 300 400 500 700 850 175 250 400 111 151 244 339 511 702 Max (2) 750 1350 1500 1925 2550 3200 3700 3850 725 1350 2225 750 1100 1650 2250 3300 4250 60 85 110 225 280 335 500 500 110 165 225 56 56 167 222 278 500 ICCAUXMIN Typ (1) Max (2) 100 125 150 300 350 425 600 600 150 200 300 100 100 250 350 500 825 Typ (1) 50 75 75 150 150 200 250 250 75 100 150 50 75 125 150 200 250 ICCOMIN Max (2) 75 100 105 250 275 300 400 400 105 150 225 75 125 225 275 300 375 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Table 5 shows the minimum current required by Virtex-4 devices for proper power-on and configuration. If the current minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. Once initialized and configured, use the XPower tool to estimate current drain on these supplies.
Notes: 1. Typical values are specified at nominal voltage, 25C. 2. Maximum values are specified under worst-case process, voltage, and temperature conditions.
Table 6: Power Supply Ramp Time Symbol VCCINT VCCO VCCAUX Description Internal supply voltage relative to GND Output drivers supply voltage relative to GND Auxiliary supply voltage relative to GND Ramp Time 0.20 to 50.0 0.20 to 50.0 0.20 to 50.0 Units ms ms ms
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 7
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
SelectIOTM DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. Table 7: SelectIO DC Input and Output Levels IOSTANDARD Attribute LVTTL LVCMOS33, LVDCI33 LVCMOS25, LVDCI25 LVCMOS18, LVDCI18 LVCMOS15, LVDCI15 PCI33_3(5) PCI66_3(5) PCI-X(5) GTLP GTL HSTL I(2) HSTL II(2) HSTL III(2) HSTL IV(2) DIFF HSTL II(2) SSTL2 I SSTL2 II DIFF SSTL2 II SSTL18 I SSTL18 II DIFF SSTL18 II VIL V, Min -0.2 -0.2 -0.3 -0.3 -0.3 -0.2 -0.2 -0.2 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 V, Max 0.8 0.8 0.7 35% VCCO 35% VCCO 30% VCCO 30% VCCO 35% VCCO VREF - 0.1 VREF - 0.05 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 50% VCCO - 0.1 VREF - 0.15 VREF - 0.15 50% VCCO - 0.15 VREF - 0.125 VREF - 0.125 50% VCCO - 0.125 V, Min 2.0 2.0 1.7 65% VCCO 65% VCCO 50% VCCO 50% VCCO 50% VCCO VREF + 0.1 VREF + 0.05 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 50% VCCO + 0.1 VREF + 0.15 VREF + 0.15 50% VCCO + 0.15 VREF + 0.125 VREF + 0.125 50% VCCO + 0.125 VIH V, Max 3.45 3.45 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO VCCO VCCO - - VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VOL V, Max 0.4 0.4 0.4 0.4 0.4 10% VCCO 10% VCCO 10% VCCO 0.6 0.4 0.4 0.4 0.4 0.4 0.4 VTT - 0.61 VTT - 0.81 0.5 VTT - 0.47 VTT - 0.60 0.4 VOH V, Min 2.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.45 VCCO - 0.45 90% VCCO 90% VCCO 90% VCCO N/A N/A VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VTT + 0.61 VTT + 0.81 VCCO - 0.5 VTT + 0.47 VTT + 0.60 VCCO - 0.4 IOL mA
Note(3) Note(3) Note(3) Note(4) Note(4)
The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
IOH mA
Note(3) Note(3) Note(3) Note(4) Note(4)
1.5 1.5 1.5 36 32 8 16 24 48 - 8.1 16.2 - 6.7 13.4 -
-0.5 -0.5 -0.5 N/A N/A -8 -16 -8 -8 - -8.1 -16.2 - -6.7 -13.4 -
Notes: 1. Tested according to relevant specifications. 2. Applies to both 1.5V and 1.8V HSTL. 3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. 4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. 5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to the Virtex-4 FPGA User Guide, SelectIO Resources, Chapter 6.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 8
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
LDT DC Specifications (LDT_25)
Table 8: LDT DC Specifications Symbol VCCO VOD VOD VOCM VOCM VID VID VICM VICM DC Parameter Supply Voltage Differential Output Voltage(1,2) Change in VOD Magnitude Output Common Mode Voltage Change in VOCM Magnitude Input Differential Voltage Change in VID Magnitude Input Common Mode Voltage Change in VICM Magnitude RT = 100 across Q and Q signals RT = 100 across Q and Q signals Conditions Min 2.38 495 -15 495 -15 200 -15 440 -15 600 600 600 Typ 2.5 600 Max 2.63 715 15 715 15 1000 15 780 15 Units V mV mV mV mV mV mV mV mV
Notes: 1. Recommended input maximum voltage not to exceed VCC0 + 0.2V. 2. Recommended input minimum voltage not to go below -0.5V.
LVDS DC Specifications (LVDS_25)
Table 9: LVDS DC Specifications Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage(1,2) (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals 0.898 247 1.125 100 0.3 350 1.250 350 1.2 454 1.375 600 2.2 Conditions Min 2.38 Typ 2.5 Max 2.63 1.602 Units V V V mV V mV V
Notes: 1. Recommended input maximum voltage not to exceed VCC0 + 0.2V. 2. Recommended input minimum voltage not to go below -0.5V.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 9
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Extended LVDS DC Specifications (LVDSEXT_25)
Table 10: Extended LVDS DC Specifications Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High Output Common-Mode Voltage RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals RT = 100 across Q and Q signals Conditions Min 2.38 - 0.715 440 1.125 100 0.3 Typ 2.5 - - - 1.250 - 1.2 Max 2.63 1.785 - 820 1.375 1000 2.2 Units V V V mV V mV V
Differential Input Voltage(1,2) Common-mode input voltage = 1.25V (Q - Q), Q = High (Q - Q), Q = High Input Common-Mode Voltage Differential input voltage = 350 mV
Notes: 1. Recommended input maximum voltage not to exceed VCC0 + 0.2V. 2. Recommended input minimum voltage not to go below -0.5V.
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower comTable 11: LVPECL DC Specifications Symbol
VOH VOL VICM VIDIFF
mon-mode ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see the Virtex-4 FPGA User Guide: Chapter 6, SelectIO Resources. Min
VCC - 1.025 VCC - 1.81 0.6 0.100
DC Parameter
Output High Voltage Output Low Voltage Input Common-Mode Voltage Differential Input Voltage(1,2)
Typ
1.545 0.795
Max
VCC - 0.88 VCC - 1.62 2.2 1.5
Units
V V V V
Notes: 1. Recommended input maximum voltage not to exceed VCC0 + 0.2V. 2. Recommended input minimum voltage not to go below -0.5V.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 10
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
RocketIO DC Input and Output Levels
Table 12 summarizes the DC input and output specifications of the Virtex-4 FPGA RocketIO Multi-Gigabit Serial Transceivers. Figure 1 shows the single-ended output voltTable 12: RocketIO DC Specifications DC Parameter
Peak-to-Peak Differential Input Voltage Single-Ended Input Range
age swing. Figure 2 shows the peak-to-peak differential output voltage. Consult the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for further details. Conditions
Internal AC Coupled Internal AC Coupled Internal AC Coupled
Symbol
DVIN SEVIN VICM VOUT VTCM DVPPOUT RXOOBVDPP TXOOBVDPP RX TX
Min
110 0 100
Typ
Max
2400 VTRX VTRX - 100
Units
mV mV mV mV
Common Mode Input Voltage Range Single-Ended Output Voltage Swing (2, 3) Common Mode Output Voltage Range (3) Peak-to-Peak Differential Output Voltage (2, 3) Signal detect threshold Electrical idle amplitude RocketIO MGT Clock DC Input Levels Peak-to-Peak Differential Input Voltage Differential Input Resistance
Bypassed Internal AC Coupled (1) 450
800 725 1000 900 1050 TBD 65 1400
mV mV mV
mV
VIDIFF RIN
2 x | VMGTCLKP - VMGTCKLN |
100 71
600 105
2000 124
mV
Notes: 1. The maximum VTRX is 1.26V when bypassing the internal AC coupled VICM. VTRX must be less than or equal to AVCCAUXRX. 2. The output swing and pre-emphasis levels are selected using the attributes discussed in Chapter 4: PMA Analog Considerations in the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for details. 3. VTTX is 1.5 5%; different amplitudes possible with adjusted DAC values.
+V
TXP DVOUT
DS302_02_031708
TXN 0
Figure 1: Single-Ended Output Voltage Swing
+V
0
DVPPOUT
-V
TXP-TXN
Figure 2: Peak-to-Peak Differential Output Voltage
DS302_03_031708
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 11
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Interface Performance Characteristics
Table 13: Interface Performance Speed Grade Description
Networking Applications SFI-4.1 (SDR LVDS Interface)(1) SPI-4.2 (DDR LVDS Interface) Memory Interfaces DDR2 SDRAM (High-Performance SERDES Design)(2) DDR2 SDRAM (Low-Latency Direct Clocking DDR SDRAM (Low-Latency Direct Clocking RLDRAM II (Low-Latency Direct Clocking Design)(3) QDRII SRAM (Low-Latency Direct Clocking Design)(4) Design)(5) Design)(6) 600 Mb/s 420 Mb/s 550 Mb/s 344 Mb/s 470 Mb/s 533 Mb/s 410 Mb/s 500 Mb/s 336 Mb/s 470 Mb/s 500 Mb/s 400 Mb/s 400 Mb/s 330 Mb/s 400 Mb/s 710 MHz 1 Gb/s 710 MHz 1 Gb/s 645 MHz 800 Mb/s
-12
-11
-10
Notes: 1. Input clocks above 622 MHz require AC coupling. 2. Performance defined using design implementation described in application note XAPP721, High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES. 3. Performance defined using design implementation described in application note XAPP702, DDR2 Controller Using Virtex-4 Devices. 4. Performance defined using design implementation described in application note XAPP703, QDR II SRAM Interface for Virtex-4 Devices. 5. Performance defined using design implementation described in application note XAPP709, DDR SDRAM Controller Using Virtex-4 FPGA Devices. 6. Performance defined using design implementation described in application note XAPP710, Synthesizable CIO DDR RLDRAM II Controller for Virtex-4 FPGAs.
Switching Characteristics
Switching characteristics are specified on a per-speedgrade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Table 14 correlates the current status of each Virtex-4 device with a corresponding speed specification version 1.68 designation.
DS302 (v3.2) April 10, 2008 Product Specification
Table 14: Virtex-4 Device Speed Grade Designations Speed Grade Designations Device
XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140
Advance
Preliminary Production
-12, -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -12, -11, -10 -11, -10
www.xilinx.com 12
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics All specifications are always representative of worst-case supply voltage and junction temperature conditions.
Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-4 devices.
PowerPC Switching Characteristics
Consult the PowerPC 405 Processor Block Reference Guide for further information. Table 15: PowerPC 405 Processor Clocks Absolute AC Characteristics Speed Grade -12 Description Characteristics when APU Not Used
CPMC405CLOCK frequency(1,4) CPMDCRCLK(3) CPMFCMCLK(3) JTAGC405TCK frequency (2) PLBCLK(3) BRAMDSOCMCLK(3) BRAMISOCMCLK(3) 0 0 NA 0 0 0 0 450 450 NA 225 450 450 450 0 0 NA 0 0 0 0 400 400 NA 200 400 400 400 0 0 NA 0 0 0 0 350 350 NA 175 350 350 350 MHz MHz MHz MHz MHz MHz MHz
-11 Max Min Max Min
-10 Max Units
Min
Characteristics when APU Used
CPMC405CLOCK frequency(1,4) CPMDCRCLK(3) CPMFCMCLK(3) JTAGC405TCK frequency(2) PLBCLK(3) BRAMDSOCMCLK(3) BRAMISOCMCLK(3) 0 0 0 0 0 0 0 333 333 333 166.5 333 333 333 0 0 0 0 0 0 0 275 275 275 137.5 275 275 275 0 0 0 0 0 0 0 233 233 233 116.5 233 233 233 MHz MHz MHz MHz MHz MHz MHz
Notes: 1. Worst-case DCM output clock jitter is included in these specifications. 2. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent, and will be much less. 3. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the CPMC405CLOCK and BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK, CPMC405CLOCK and CPMFCMCLK, and CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However, the achievable maximum is system dependent. 4. Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic 1.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 13
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 16: Processor Block Switching Characteristics
Speed Grade Description
Setup and Hold Relative to Clock (CPMC405CLOCK) Clock and Power Management control inputs Reset control inputs Debug control inputs Trace control inputs External Interrupt Controller control inputs Clock to Out Clock and Power Management control outputs Reset control outputs Debug control outputs Trace control outputs Clock CPMC405CLOCK minimum pulse width, High CPMC405CLOCK minimum pulse width, Low TCPWH TCPWL 1.11 1.11 1.25 1.25 1.43 1.43 ns, Min ns, Min TPPCCKO_CORESLP TPPCCKO_RSTCHIP TPPCCKO_DBGLDAPU TPPCCKO_TRCCYCLE 1.35 1.44 1.34 1.52 1.51 1.59 1.48 1.68 1.74 1.83 1.70 1.83 ns, Max ns, Max ns, Max ns, Max TPPCDCK_CORECKI/ TPPCCKD_CORECKI TPPCDCK_RSTCHIP/ TPPCCKD_RSTCHIP TPPCDCK_EXBUSHAK/ TPPCCKD_EXBUSHAK TPPCDCK_TRCDIS/ TPPCCKD_TRCDIS TPPCDCK_CINPIRQ/ TPPCCKD_CINPIRQ 0.60 0.20 0.60 0.20 0.60 0.20 0.60 0.20 1.04 0.20 0.65 0.20 0.65 0.20 0.65 0.20 0.65 0.20 1.15 0.20 0.74 0.23 0.74 0.23 0.74 0.23 0.74 0.23 1.40 0.23 ns, Min ns, Min ns, Min ns, Min ns, Min
Symbol
-12
-11
-10
Units
Table 17: Processor Block PLB Switching Characteristics
Speed Grade Description
Setup and Hold Relative to Clock (PLBCLK) Processor Local Bus (ICU/DCU) control inputs Processor Local Bus (ICU/DCU) data inputs Clock to Out Processor Local Bus (ICU/DCU) control outputs Processor Local Bus (ICU/DCU) address bus outputs Processor Local Bus (ICU/DCU) data bus outputs TPPCCKO_DCUABORT TPPCCKO_ICUABUS TPPCCKO_DCUWRDBUS 1.61 1.66 2.08 1.78 1.85 2.24 2.05 2.13 2.57 ns, Max ns, Max ns, Max TPPCDCK_ICUBUSY/ TPPCCKD_ICUBUSY TPPCDCK_ICURDDB/ TPPCCKD_ICURDDB 0.60 0.20 0.90 0.20 0.66 0.20 1.00 0.20 0.76 0.23 1.15 0.23 ns, Min ns, Min
Symbol
-12
-11
-10
Units
Table 18: Processor Block JTAG Switching Characteristics
Speed Grade Description
Setup and Hold Relative to Clock (JTAGC405TCK) JTAG control inputs JTAG reset input Clock to Out JTAG control outputs TPPCCKO_JTGTDO 1.68 1.79 2.14 ns, Max TPPCDCK_JTGTDI TPPCCKD_JTGTDI TPPCDCK_JTGTRSTN TPPCCKD_JTGTRSTN 1.16 0.20 0.60 0.20 1.29 0.20 0.65 0.20 1.48 0.23 0.74 0.23 ns, Min ns, Min
Symbol
-12
-11
-10
Units
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 14
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 19: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (BRAMDSOCMCLK) Data-Side On-Chip Memory data bus inputs Clock to Out Data-Side On-Chip Memory control outputs Data-Side On-Chip Memory address bus outputs Data-Side On-Chip Memory data bus outputs TPPCCKO_BRAMBWR TPPCCKO_BRAMABUS TPPCCKO_IBRAMWRDBUS01 2.07 2.07 1.61 2.30 2.30 1.79 2.65 2.65 2.06 ns, Max ns, Max ns, Max TPPCDCK_DSOCMRDDB TPPCCKD_DSOCMRDDB 0.60 0.20 0.65 0.20 0.74 0.23 ns, Min
Symbol
-12
-11
-10
Units
Table 20: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (BRAMISOCMCLK) Instruction-Side On-Chip Memory data bus inputs Clock to Out Instruction-Side On-Chip Memory control outputs Instruction-Side On-Chip Memory address bus outputs Instruction-Side On-Chip Memory data bus outputs TPPCCKO_IBRAMEN TPPCCKO_IBRAMRDABUS TPPCCKO_IBRAMWRDBUS 3.04 1.67 1.67 3.37 1.85 1.86 3.88 2.13 2.14 ns, Max ns, Max ns, Max TPPCDCK_ISOCMRDDB TPPCCKD_ISOCMRDDB 0.74 0.20 0.82 0.20 0.94 0.23 ns, Min
Symbol
-12
-11
-10
Units
Table 21: Processor Block DCR Bus Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (CPMDCRCLOCK) Device Control Register Bus control inputs Device Control Register Bus data inputs Clock to Out Device Control Register Bus control outputs Device Control Register Bus address bus outputs Device Control Register Bus data bus outputs TPPCCKO_EXDCRRD TPPCCKO_EXDCRABUS TPPCCKO_EXDCRDBUSO 1.20 1.28 1.31 1.35 1.45 1.45 1.54 1.66 1.67 ns, Max ns, Max ns, Max TPPCDCK_EXDCRACK TPPCCKD_EXDCRACK TPPCDCK_EXDCRDBUSI TPPCCKD_EXDCRDBUSI 0.12 0.15 0.57 0.16 0.13 0.17 0.57 0.16 0.15 0.19 1.02 0.27 ns, Min ns, Min
Symbol
-12
-11
-10
Units
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 15
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 22: Processor Block APU Interface Switching Characteristics Speed Grade Description
Setup and Hold Relative to Clock (CPMDFCMCLOCK) APU bus control inputs APU bus data inputs Clock to Out APU bus control outputs APU bus data outputs TPPCCKO_APUFCMDEC TPPCCKO_RADATA 1.53 1.53 1.75 1.75 2.00 2.00 ns, Max ns, Max TPPCDCK_DCDCREN TPPCCKD_DCDCREN TPPCDCK_RESULT TPPCCKD_RESULT 0.33 0.20 0.61 0.20 0.36 0.20 0.67 0.20 0.42 0.23 0.78 0.23 ns, Min ns, Min
Symbol
-12
-11
-10
Units
RocketIO Switching Characteristics
Consult the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for further information. Table 23: Maximum RocketIO Transceiver Performance Speed Grade Description RocketIO Transceiver Table 24: RocketIO Reference Clock Switching Characteristics
All Speed Grades Description
Reference Clock frequency range(1) GREFCLK Reference Clock frequency Reference Clock frequency tolerance Reference Clock rise time Reference Clock fall time Reference Clock duty cycle Reference Clock total jitter, peak-peak (2) range(1)
-12 6.5
-11 6.5
-10 3.125
Units Gb/s
Symbol
FGCLK FGREFCLK FGTOL TRCLK TFCLK TDCREF TGJTT TLOCK CLK CLK CLK
Conditions
Min
106 106 -350
Typ
Max
644 320 +350 400 400
Units
MHz MHz ppm ps ps % ps ms
20% - 80% 20% - 80% CLK CLK Initial lock of the PLL from startup (programmable) Lock to data after PLL has relocked to the reference clock. Includes lock to reference time (programmable) 0% to -0.5% 30 1 45
55 40
Clock recovery frequency acquisition time
Clock recovery phase acquisition time Spread Spectrum Clocking (3)
TPHASE
33
kHz
Notes: 1. MGTCLK input can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s. 2. Measured at the package pin. For serial rates equal to or above 1 Gb/s, MGTCLK must be used. UI = Unit Interval. 3. Tested with synchronous reference clock.
TRCLK
80%
20%
TFCLK
DS302_04_031708
Figure 3: Reference Clock Timing Parameters
DS302 (v3.2) April 10, 2008 Product Specification www.xilinx.com 16
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 25: RocketIO Receiver Switching Characteristics
Description Serial data rate, -10 Serial data rate, -11 Receive Deterministic Jitter Tolerance Receive Total Jitter Tolerance Receive Sinusoidal Jitter Tolerance General Receive Jitter Tolerance Symbol FGRX FGRX Rate (Gb/s) Mode (3) 3.125 3.125 3.125 TSJTOL
(7)
Conditions
Min 0.622 0.622 Frequency
Typ
Max 3.125 6.5 0.37 0.65
Units Gb/s Gb/s
XAUI Receive Jitter Tolerance (8B/10B CJPAT) (2) TDJTOL TTJTOL
(6)
ACDR ACDR ACDR ACDR ACDR Mode(3) ACDR ACDR ACDR ACDR ACDR ACDR DCDR DCDR DCDR ACDR ACDR ACDR ACDR ACDR ACDR DCDR DCDR DCDR f = 22.1 kHz f = 1.875 MHz f = 20 MHz Pattern PRBS7 PRBS7 PRBS7 PRBS7 PRBS7 PRBS7 PRBS7 PRBS31 PRBS31 PRBS7 PRBS7 PRBS7 PRBS7 PRBS7 PRBS7 PRBS7 PRBS31 PRBS31
8.5 0.10 0.10 0.65 0.65 0.65 0.60 0.55 0.50 0.50 0.40 0.40 0.65 0.65 0.65 0.50 0.50 0.50 0.55 0.35 0.55 250 250 40 40 110 30 60 60 20
UI (1)
3.125 3.125 Rate (Gb/s) 6.5(5) 5.0(5) 4.25(5) 3.125
Receive deterministic jitter tolerance
TDJTOL
(2,4)
2.5 1.25 1.25 1.25 0.622 6.5(9) 5.0(9) 4.25(9) 3.125 (8)
UI (1)
Sinusoidal jitter tolerance
TSJTOL
2.5(8) 1.25(8) 1.25(8) 1.25(8) 0.622(8)
RXUSRCLK frequency RXUSRCLK2 frequency RXUSRCLK duty cycle RXUSRCLK2 duty cycle Differential input skew Differential receive input sensitivity(2) On-chip AC coupling corner frequency Signal detect response time Input capacitance at the Die Excess capacitance at the solder ball
TRX TRX2 TRXDC TRX2DC TISKEW VEYE
For slower speed grades = MaxDataRate/32
MHz MHz % % ps mV ns fF fF
RXSIGDETResponsetime CDIE CBALL
6. 7. 8. 9.
Notes: 1. UI = Unit Interval 2. Using receiver equalization setting of 111 (14 dB). 3. ACDR = Analog CDR and DCDR = Digital CDR. 4. Deterministic jitter (DJ) is composed of 75% ISI + 25% high frequency sinusoidal jitter (SJ). 5. Deterministic Jitter (DJ) composed of ISI + 0.10 UI of high frequency SJ + 0.15 UI of RJ.
Sum of DJ, random jitter (RJ) of at least 0.55 UI, and sinusoidal jitter as defined by mask in IEEE Std 802.3ae-2002, Figure 47-5. SJ in addition to 0.55 UI of DJ +RJ. Jitter frequency = 5 MHz. Jitter frequency = 10 MHz.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 17
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 26: RocketIO Transmitter Switching Characteristics
Description
Serial data rate, -10 Serial data rate, -11
Symbol
FGTX FGTX
Conditions
Min 0.622 0.622
Typ
Max 3.125 6.5 0.50
Units Gb/s Gb/s
Data
Rate (Gb/s)
TJ RJ DJ TJ RJ DJ TJ RJ DJ TJ
TX Jitter Generation (3) PRBS7 4.25 PRBS7 5.0 PRBS7 6.5
0.35 0.30 0.45 0.30 0.25 0.40 0.25 0.21 0.28 UI (1)
RJ DJ TJ RJ DJ TJ RJ DJ TJ RJ DJ
PRBS7
3.125
0.14 0.14 0.25
PRBS7
2.5
0.18 0.12 0.12
PRBS7
1.25
0.10 0.06 0.08
PRBS31
0.622
0.06 0.04
TX rise
time(2)
TRTX TFTX
20% - 80% 20% - 80% For slower speed grades = MaxDataRate/32
90 90 250 250
ps ps MHz MHz % % ps ns
TX fall time(2) TXUSRCLK frequency TXUSRCLK2 frequency TXUSRCLK duty cycle TXUSRCLK2 duty cycle Differential output skew Electrical idle transition time
TTXDC TTX2DC TISKEW TXOOBTransition
40 40 12 15
60 60 20
Notes: 1. UI = Unit Interval. 2. Default attributes, measured at 2.5 Gb/s. 3. Peak-to-Peak values measured relative to 1e-12 Error rate. Default attributes. TX feedback divider (TXPLLNDIVSEL) = 10.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 18
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
IOB Pad Input/Output/3-State Switching Characteristics
Table 27 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. Table 27: IOB Switching Characteristics(1,2) TIOPI IOSTANDARD Attribute(1) -12
LVDS_25 RSDS_25 LVDSEXT_25 LDT_25 BLVDS_25 ULVDS_25 PCI33_3 (PCI, 33 MHz, 3.3V) PCI66_3 (PCI, 66 MHz, 3.3V) PCI-X GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I _18 HSTL_II _18 HSTL_III _18 HSTL_IV_18 SSTL2_I SSTL2_II LVTTL, Slow, 2 mA LVTTL, Slow, 4 mA LVTTL, Slow, 6 mA LVTTL, Slow, 8 mA 1.00 1.00 1.01 1.00 1.00 1.00 0.76 0.76 0.76 1.28 1.31 1.28 1.28 1.28 1.28 1.26 1.26 1.26 1.26 1.31 1.31 0.76 0.76 0.76 0.76 Speed Grade
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 28 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
TIOOP
Speed Grade
TIOTP
Speed Grade
Units -10
1.85 1.85 1.91 1.82 2.34 1.83 3.02 2.72 2.25 2.03 2.03 2.35 2.13 2.22 2.03 2.21 2.16 2.09 2.06 2.43 2.16 7.03 5.04 4.91 4.91 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-11
1.15 1.15 1.16 1.15 1.15 1.15 0.87 0.87 0.87 1.47 1.51 1.47 1.47 1.47 1.47 1.44 1.44 1.44 1.44 1.51 1.51 0.87 0.87 0.87 0.87
-10
1.28 1.28 1.30 1.28 1.28 1.28 0.97 0.97 0.97 1.63 1.68 1.64 1.64 1.64 1.64 1.60 1.60 1.60 1.60 1.68 1.68 0.97 0.97 0.97 0.97
-12
1.61 1.61 1.65 1.58 1.99 1.59 2.52 2.22 2.19 1.75 1.75 2.00 1.83 1.90 1.75 1.89 1.85 1.80 1.77 2.06 1.85 5.66 4.10 4.00 4.00
-11
1.71 1.71 1.75 1.68 2.15 1.68 2.76 2.46 2.21 1.87 1.87 2.16 1.96 2.04 1.87 2.03 1.98 1.93 1.89 2.23 1.98 6.37 4.57 4.46 4.46
-10
1.85 1.85 1.91 1.82 2.34 1.83 3.02 2.72 2.25 2.03 2.03 2.35 2.13 2.22 2.03 2.21 2.16 2.09 2.06 2.43 2.16 7.03 5.04 4.91 4.91
-12
1.61 1.61 1.65 1.58 1.99 1.59 2.52 2.22 2.19 1.75 1.75 2.00 1.83 1.90 1.75 1.89 1.85 1.80 1.77 2.06 1.85 5.66 4.10 4.00 4.00
-11
1.71 1.71 1.75 1.68 2.15 1.68 2.76 2.46 2.21 1.87 1.87 2.16 1.96 2.04 1.87 2.03 1.98 1.93 1.89 2.23 1.98 6.37 4.57 4.46 4.46
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 19
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 27: IOB Switching Characteristics(1,2) (Continued) TIOPI IOSTANDARD Attribute(1) -12
LVTTL, Slow, 12 mA LVTTL, Slow, 16 mA LVTTL, Slow, 24 mA LVTTL, Fast, 2 mA LVTTL, Fast, 4 mA LVTTL, Fast, 6 mA LVTTL, Fast, 8 mA LVTTL, Fast, 12 mA LVTTL, Fast, 16 mA LVTTL, Fast, 24 mA LVCMOS33, Slow, 2 mA LVCMOS33, Slow, 4 mA LVCMOS33, Slow, 6 mA LVCMOS33, Slow, 8 mA LVCMOS33, Slow, 12 mA LVCMOS33, Slow, 16 mA LVCMOS33, Slow, 24 mA LVCMOS33, Fast, 2 mA LVCMOS33, Fast, 4 mA LVCMOS33, Fast, 6 mA LVCMOS33, Fast, 8 mA LVCMOS33, Fast, 12 mA LVCMOS33, Fast, 16 mA LVCMOS33, Fast, 24 mA LVCMOS25, Slow, 2 mA LVCMOS25, Slow, 4 mA LVCMOS25, Slow, 6 mA LVCMOS25, Slow, 8 mA LVCMOS25, Slow, 12 mA LVCMOS25, Slow, 16 mA LVCMOS25, Slow, 24 mA LVCMOS25, Fast, 2 mA LVCMOS25, Fast, 4 mA LVCMOS25, Fast, 6 mA LVCMOS25, Fast, 8 mA LVCMOS25, Fast, 12 mA 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.76 0.69 0.69 0.69 0.69 0.69 0.69 0.69 0.69 0.69 0.69 0.69 0.69 Speed Grade
TIOOP
Speed Grade
TIOTP
Speed Grade
Units -10
3.96 3.46 3.12 4.86 3.46 3.00 2.79 2.47 2.47 2.20 8.73 6.09 5.00 3.95 3.42 2.49 2.49 7.44 4.33 3.55 2.46 2.27 2.08 2.08 5.89 5.02 4.31 4.31 3.50 3.31 2.77 3.89 3.19 2.81 2.52 2.43 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-11
0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.87 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80
-10
0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.88 0.88 0.88 0.88 0.88 0.88 0.88 0.88 0.88 0.88 0.88 0.88
-12
3.26 2.87 2.60 3.96 2.87 2.51 2.34 2.09 2.09 1.88 6.98 4.92 4.07 3.25 2.83 2.11 2.11 5.98 3.55 2.93 2.09 1.93 1.79 1.79 4.77 4.09 3.53 3.53 2.90 2.75 2.33 3.20 2.66 2.36 2.13 2.06
-11
3.61 3.16 2.85 4.41 3.16 2.74 2.55 2.26 2.26 2.02 7.88 5.52 4.54 3.59 3.11 2.28 2.28 6.73 3.93 3.23 2.25 2.08 1.91 1.91 5.34 4.56 3.92 3.92 3.19 3.02 2.54 3.54 2.92 2.57 2.31 2.23
-10
3.96 3.46 3.12 4.86 3.46 3.00 2.79 2.47 2.47 2.20 8.73 6.09 5.00 3.95 3.42 2.49 2.49 7.44 4.33 3.55 2.46 2.27 2.08 2.08 5.89 5.02 4.31 4.31 3.50 3.31 2.77 3.89 3.19 2.81 2.52 2.43
-12
3.26 2.87 2.60 3.96 2.87 2.51 2.34 2.09 2.09 1.88 6.98 4.92 4.07 3.25 2.83 2.11 2.11 5.98 3.55 2.93 2.09 1.93 1.79 1.79 4.77 4.09 3.53 3.53 2.90 2.75 2.33 3.20 2.66 2.36 2.13 2.06
-11
3.61 3.16 2.85 4.41 3.16 2.74 2.55 2.26 2.26 2.02 7.88 5.52 4.54 3.59 3.11 2.28 2.28 6.73 3.93 3.23 2.25 2.08 1.91 1.91 5.34 4.56 3.92 3.92 3.19 2.02 2.54 3.54 2.92 2.57 2.31 2.23
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 20
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 27: IOB Switching Characteristics(1,2) (Continued) TIOPI IOSTANDARD Attribute(1) -12
LVCMOS25, Fast, 16 mA LVCMOS25, Fast, 24 mA LVCMOS18, Slow, 2 mA LVCMOS18, Slow, 4 mA LVCMOS18, Slow, 6 mA LVCMOS18, Slow, 8 mA LVCMOS18, Slow, 12 mA LVCMOS18, Slow, 16 mA LVCMOS18, Fast, 2 mA LVCMOS18, Fast, 4 mA LVCMOS18, Fast, 6 mA LVCMOS18, Fast, 8 mA LVCMOS18, Fast, 12 mA LVCMOS18, Fast, 16 mA LVCMOS15, Slow, 2 mA LVCMOS15, Slow, 4 mA LVCMOS15, Slow, 6 mA LVCMOS15, Slow, 8 mA LVCMOS15, Slow, 12 mA LVCMOS15, Slow, 16 mA LVCMOS15, Fast, 2 mA LVCMOS15, Fast, 4 mA LVCMOS15, Fast, 6 mA LVCMOS15, Fast, 8 mA LVCMOS15, Fast, 12 mA LVCMOS15, Fast, 16 mA LVDCI_33 LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 GTL_DCI (3) GTLP_DCI (3) HSTL_I_DCI (3) 0.69 0.69 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 0.97 1.05 1.05 1.05 1.05 1.05 1.05 1.05 1.05 1.05 1.05 1.05 1.05 0.76 0.69 0.97 1.05 0.69 0.97 1.05 1.18 0.96 1.28 Speed Grade
TIOOP
Speed Grade
TIOTP
Speed Grade
Units -10
2.21 2.13 5.89 4.35 4.00 3.76 3.74 3.55 3.89 3.02 2.72 2.52 2.36 2.27 6.61 4.88 4.26 4.26 3.77 3.53 4.17 3.32 2.94 2.71 2.50 2.43 3.13 3.02 2.95 2.93 2.27 2.28 2.58 2.03 2.03 2.35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-11
0.80 0.80 1.12 1.12 1.12 1.12 1.12 1.12 1.12 1.12 1.12 1.12 1.12 1.12 1.20 1.20 1.20 1.20 1.20 1.20 1.20 1.20 1.20 1.20 1.20 1.20 0.87 0.80 1.12 1.20 0.80 1.12 1.20 1.36 1.11 1.47
-10
0.88 0.88 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 0.97 0.88 1.25 1.34 0.88 1.25 1.34 1.51 1.23 1.64
-12
1.89 1.83 4.77 3.56 3.29 3.10 3.09 2.94 3.20 2.52 2.29 2.13 2.01 1.94 5.33 4.21 3.49 3.49 3.11 2.92 3.42 2.76 2.46 2.28 2.12 2.06 2.61 2.52 2.47 2.45 1.93 1.95 2.18 1.75 1.75 2.00
-11
2.03 1.96 5.34 3.95 3.64 3.42 3.41 3.24 3.54 2.75 2.49 2.31 2.17 2.09 5.99 4.70 3.87 3.87 3.43 3.21 3.79 3.03 2.69 2.48 2.29 2.23 2.86 2.76 2.69 2.68 2.08 2.09 2.36 1.87 1.87 2.16
-10
2.21 2.13 5.89 4.35 4.00 3.76 3.74 3.55 3.89 3.02 2.72 2.52 2.36 2.27 6.61 4.88 4.26 4.26 3.77 3.53 4.17 3.32 2.94 2.71 2.50 2.43 3.13 3.02 2.95 2.93 2.27 2.28 2.58 2.03 2.03 2.35
-12
1.89 1.83 4.77 3.56 3.29 3.10 3.09 2.94 3.20 2.52 2.29 2.13 2.01 1.94 5.33 4.21 3.49 3.49 3.11 2.92 3.42 2.76 2.46 2.28 2.12 2.06 2.61 2.52 2.47 2.45 1.93 1.95 2.18 1.75 1.75 2.00
-11
2.03 1.96 5.34 3.95 3.64 3.42 3.41 3.24 3.54 2.75 2.49 2.31 2.17 2.09 5.99 4.70 3.87 3.87 3.43 3.21 3.79 3.03 2.69 2.48 2.29 2.23 2.86 2.76 2.69 2.68 2.08 2.09 2.36 1.87 1.87 2.16
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 21
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 27: IOB Switching Characteristics(1,2) (Continued) TIOPI IOSTANDARD Attribute(1) -12
HSTL_II_DCI (3) HSTL_III_DCI (3) HSTL_IV_DCI (3) HSTL_I_DCI_18 (3) HSTL_II_DCI_18 (3) HSTL_III_DCI_18 (3) HSTL_IV_DCI_18 (3) SSTL2_I_DCI (3) SSTL2_II_DCI (3) LVPECL_25 SSTL18_I SSTL18_II SSTL18_I_DCI (3) SSTL18_II_DCI (3) 1.28 1.28 1.28 1.26 1.26 1.26 1.26 1.31 1.31 1.38 1.31 1.31 1.31 1.31 Speed Grade
TIOOP
Speed Grade
TIOTP
Speed Grade
Units -10
2.13 2.22 2.03 2.21 2.16 2.09 2.06 2.46 2.45 1.74 2.54 2.24 2.32 2.18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-11
1.47 1.47 1.47 1.44 1.44 1.44 1.44 1.51 1.51 1.59 1.51 1.51 1.51 1.51
-10
1.64 1.64 1.64 1.60 1.60 1.60 1.60 1.68 1.68 1.77 1.68 1.68 1.68 1.68
-12
1.83 1.90 1.75 1.89 1.85 1.80 1.77 2.09 2.07 1.52 2.15 1.92 1.97 1.87
-11
1.96 2.04 1.87 2.03 1.98 1.93 1.89 2.25 2.24 1.61 2.33 2.06 2.12 2.00
-10
2.13 2.22 2.03 2.21 2.16 2.09 2.06 2.46 2.45 1.74 2.54 2.24 2.32 2.18
-12
1.83 1.90 1.75 1.89 1.85 1.80 1.77 2.09 2.07 1.52 2.15 1.92 1.97 1.87
-11
1.96 2.04 1.87 2.03 1.98 1.93 1.89 2.25 2.24 1.61 2.33 2.06 2.12 2.00
Notes: 1. The I/O standard is selected in the Xilinx ISE(R) software tool using the IOSTANDARD attribute. 2. All I/O timing specifications are measured with VCCO at -5% from nominal. 3. The values of the DCI reference resistors must be within a 20-100 range. Refer to UG070, Virtex-4 FPGA User Guide, for detailed information.
Table 28: IOB 3-state ON Output Switching Characteristics (TIOTPHZ) Speed Grade Symbol
TIOTPHZ
Description
T input to Pad high-impedance
-12
0.88
-11
1.01
-10
1.12
Units
ns
Ethernet MAC Switching Characteristics
Consult UG074: Virtex-4 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information. Table 29: Maximum Ethernet MAC Performance Speed Grade Description
Ethernet MAC Maximum Performance
-12
-11
10/100/1000
-10
Units
Mb/s
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 22
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 30 shows the test setup parameters used for measuring input delay. Table 30: Input Delay Measurement Methodology
I/O Standard
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus HSTL (High-Speed Transceiver Logic), Class I & II HSTL, Class III & IV HSTL, Class I & II, 1.8V HSTL, Class III & IV, 1.8V SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL, Class I & II, 2.5V SSTL, Class I & II, 1.8V AGP-2X/AGP (Accelerated Graphics Port) LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V ULVDS (Ultra LVDS), 2.5V LDT (HyperTransport), 2.5V LVTTL
Attribute
LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PCI33_3 PCI66_3 PCIX GTL GTLP HSTL_I, HSTL_II HSTL_III, HSTL_IV HSTL_I_18, HSTL_II_18 HSTL_III_18, HSTL_IV_18 SSTL3_I, SSTL3_II SSTL2_I, SSTL2_II SSTL18_I, SSTL18_II AGP LVDS_25 LVDSEXT_25 ULVDS_25 LDT_25
VL (1,2)
0 0 0 0 0
VH (1,2)
3.0 3.3 2.5 1.8 1.5
VMEAS
(1,4,5)
VREF (1,3,5)
- - - - - - - -
1.4 1.65 1.25 0.9 0.75
Per PCI Specification Per PCI Specification Per PCI-X Specification VREF - 0.2 VREF - 0.2 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 1.00 VREF - 0.75 VREF - 0.5 VREF - (0.2 xVCCO) 1.2 - 0.125 1.2 - 0.125 0.6 - 0.125 0.6 - 0.125 VREF + 0.2 VREF + 0.2 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 1.00 VREF + 0.75 VREF + 0.5 VREF + (0.2 xVCCO) 1.2 + 0.125 1.2 + 0.125 0.6 + 0.125 0.6 + 0.125 VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF 1.2 1.2 0.6 0.6
0.80 1.0 0.75 0.90 0.90 1.08 1.5 1.25 0.90 AGP Spec
Notes: 1. Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage. Parameters for all other DCI standards are the same as for the corresponding non-DCI standards. 2. Input waveform switches between VLand VH. 3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 4. Input voltage level from which measurement starts. 5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 4.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 23
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4 inches of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4 inch trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setup shown in Figure 4. Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: 1. Simulate the output driver of choice into the generalized test setup, using values from Table 31. 2. Record the time to VMEAS . 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to VMEAS . 5. Compare the results of steps 2 and 4. The increase or decrease in delay yields the actual worst-case propagation delay (clock-to-input) of the PCB trace.
VREF
FPGA Output
RREF
VMEAS
(voltage level when taking delay measurement)
CREF
(probe capacitance)
DS302_05_031708
Figure 4: Generalized Test Setup Table 31: Output Delay Measurement Methodology Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVCMOS, 1.2V PCI (Peripheral Component Interface), 33 MHz, 3.3V
I/O Standard Attribute
LVTTL (all) LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 (rising edge) PCI33_3 (falling edge) PCI66_3 (rising edge) PCI66_3 (falling edge) PCIX (rising edge) PCIX (falling edge GTL GTLP HSTL_I HSTL_II HSTL_III HSTL_IV HSTL_I_18 HSTL_II_18 HSTL_III_18
RREF ()
1M 1M 1M 1M 1M 1M 25 25 25 25 25 25 25 25 50 25 50 25 50 25
CREF(1) (pF)
0 0 0 0 0 0 10 (2) 10 (2) 10 (2) 10 (2) 10 (3) 10 (3) 0 0 0 0 0 0 0 0
VMEAS (V)
1.4 1.65 1.25 0.9 0.75 0.75 0.94 2.03 0.94 2.03 0.94 2.03 0.8 1.0 VREF VREF 0.9 0.9 VREF VREF
VREF (V)
0 0 0 0 0 0 0 3.3 0 3.3
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V GTL (Gunning Transceiver Logic) GTL Plus HSTL (High-Speed Transceiver Logic), Class I HSTL, Class II HSTL, Class III HSTL, Class IV HSTL, Class I, 1.8V HSTL, Class II, 1.8V HSTL, Class III, 1.8V
3.3 1.2 1.5 0.75 0.75 1.5 1.5 0.9 0.9
50
0
1.1
1.8
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 24
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 31: Output Delay Measurement Methodology (Continued) Description
HSTL, Class IV, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V BLVDS (Bus LVDS), 2.5V LDT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVDCI/HSLVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI/HSLVDCI, 2.5V LVDCI/HSLVDCI, 1.8V LVDCI/HSLVDCI, 1.5V HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL, Class III & IV, with DCI HSTL, Class I & II, 1.8V, with DCI HSTL, Class III & IV, 1.8V, with DCI SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL, Class I & II, 2.5V, with DCI GTL (Gunning Transceiver Logic) with DCI GTL Plus with DCI
Notes: 1. CREF is the capacitance of the probe, nominally 0 pF. 2. Per PCI specifications. 3. Per PCI-X specifications.
I/O Standard Attribute
HSTL_IV_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II LVDS_25 LVDSEXT_25 BLVDS_25 LDT_25 LVPECL_25 LVDCI_33, HSLVDCI_33 LVDCI_25, HSLVDCI_25 LVDCI_18, HSLVDCI_18 LVDCI_15, HSLVDCI_15 HSTL_I_DCI, HSTL_II_DCI HSTL_III_DCI, HSTL_IV_DCI HSTL_I_DCI_18, HSTL_II_DCI_18 HSTL_III_DCI_18, HSTL_IV_DCI_18 SSTL18_I_DCI, SSTL18_II_DCI SSTL2_I_DCI, SSTL2_II_DCI GTL_DCI GTLP_DCI
RREF ()
25 50 25 50 25 50 50 1M 50 1M 1M 1M 1M 1M 50 50 50 50 50 50 50 50
CREF(1) (pF)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VMEAS (V)
1.1 VREF VREF VREF VREF VREF VREF 1.2 VREF 0.90 1.65 1.25 0.9 0.75 VREF 0.9 VREF 1.1 VREF VREF 0.8 1.0
VREF (V)
1.8 0.9 0.9 1.25 1.25 1.2 1.2 0 0.6 0 0 0 0 0 0.75 1.5 0.9 1.8 0.9 1.25 1.2 1.5
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 25
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 32: ILOGIC Switching Characteristics Speed Grade Symbol
Setup/Hold TICE1CK / TICKCE1 TICECK / TICKCE TIRSTCK / TICKRST TIINCCK / TICKINC TISRCK / TICKSR TIDOCK / TIOCKD CE1 pin Setup/Hold with respect to CLK DLYCE pin Setup/Hold with respect to C DLYRST pin Setup/Hold with respect to C DLYINC pin Setup/Hold with respect to C SR/REV pin Setup/Hold with respect to CLK D pin Setup/Hold with respect to CLK without Delay D pin Setup/Hold with respect to CLK (IOBDELAY_TYPE = DEFAULT) D pin Setup/Hold with respect to CLK (IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) (1) 0.58 -0.23 0.16 0.11 -0.03 0.37 0.01 0.36 1.15 -0.56 0.24 -0.10 6.64 -5.99 0.81 -0.63 0.66 -0.23 0.19 0.13 -0.02 0.45 0.01 0.43 1.33 -0.56 0.28 -0.10 7.63 -5.99 0.87 -0.63 0.79 -0.23 0.23 0.16 -0.02 0.54 0.01 0.51 1.59 -0.56 0.34 -0.10 8.84 -5.99 1.09 -0.63 ns ns ns ns ns ns ns ns
Description
-12
-11
-10
Units
TIDOCKD / TIOCKDD
Combinatorial TIDI D pin to O pin propagation delay, no Delay D pin to O pin propagation delay (IOBDELAY_TYPE = DEFAULT) TIDID D pin to O pin propagation delay (IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) (1) 0.17 6.00 0.74 0.20 6.91 0.79 0.24 7.96 0.99 ns ns ns
Sequential Delays TIDLO D pin to Q1 pin using flip-flop as a latch without Delay D pin to Q1 pin using flip-flop as a latch (IOBDELAY_TYPE = DEFAULT) TIDLOD D pin to Q1 pin using flip-flop as a latch (IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) (1) CLK to Q outputs CE1 pin to Q1 using flip-flop as a latch, propagation delay SR/REV pin to OQ/TQ out Global Set/Reset to Q outputs 0.50 6.90 1.07 0.53 0.90 1.70 1.54 0.59 7.94 1.18 0.60 1.06 2.03 1.73 0.71 9.21 1.45 0.72 1.27 2.44 2.03 ns ns ns ns ns ns ns
TICKQ TICE1Q TRQ TGSRQ Set/Reset TRPW
Minimum Pulse Width, SR/REV inputs
0.53
0.59
0.70
ns, Min
Notes: 1. Recorded at 0 tap value. Refer to Timing Report for other values.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 26
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 33: OLOGIC Switching Characteristics Speed Grade Symbol
Setup/Hold TODCK / TOCKD TOOCECK / TOCKOCE TOSRCK / TOCKSR TOTCK / TOCKT TOTCECK / TOCKTCE Combinatorial TODQ TOTQ Sequential Delays TIOSRON TOCKQ TRQ TGSRQ Set/Reset TRPW Minimum Pulse Width, SR/REV inputs 0.53 0.59 0.70 ns, Min REV pin to TQ out CLK to OQ/TQ out SR/REV pin to OQ/TQ out Global Set/Reset to Q outputs 1.14 0.41 1.14 1.54 1.37 0.49 1.37 1.73 1.64 0.59 1.64 2.03 ns ns ns ns D1 to OQ out T1 to TQ out 0.56 0.56 0.65 0.65 0.76 0.76 ns ns D1/D2 pins Setup/Hold with respect to CLK OCE pin Setup/Hold with respect to CLK SR/REV pin Setup/Hold with respect to CLK T1/T2 pins Setup/Hold with respect to CLK TCE pin Setup/Hold with respect to CLK 0.52 -0.22 0.53 -0.33 0.99 -0.55 0.52 -0.22 0.53 -0.33 0.62 -0.22 0.64 -0.33 1.18 -0.55 0.62 -0.22 0.64 -0.33 0.75 -0.22 0.77 -0.33 1.42 -0.55 0.75 -0.22 0.77 -0.33 ns ns ns ns ns
Description
-12
-11
-10
Units
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 27
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 34: ISERDES Switching Characteristics Speed Grade Symbol
Setup/Hold for Control Lines TISCCK_BITSLIP / TISCKC_BITSLIP TISCCK_CE / TISCKC_CE(2) TISCCK_CE2 / TISCKC_CE2(2) TISCCK_DLYCE / TISCKC_DLYCE TISCCK_DLYINC / TISCKC_DLYINC TISCCK_DLYRST / TISCKC_DLYRST TISCCK_SR Setup/Hold for Data Lines D pin Setup/Hold with respect to CLK (IOBDELAY = IBUF or NONE) TISDCK_D / TISCKD_D D pin Setup/Hold with respect to CLK (IOBDELAY = IFD or BOTH, IOBDELAY_TYPE = DEFAULT) D pin Setup/Hold with respect to CLK(1) (IOBDELAY = IFD or BOTH, IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) D pin Setup/Hold with respect to CLK at DDR mode (IOBDELAY = IBUF or NONE) TISDCK_DDR / TISCKD_DDR D pin Setup/Hold with respect to CLK at DDR mode (IOBDELAY = IFD or BOTH, IOBDELAY_TYPE = DEFAULT) D pin Setup/Hold with respect to CLK at DDR mode(1) (IOBDELAY = IFD or BOTH, IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) Sequential Delays TISCKO_Q Propagation Delays TISDO_DO_IOBDELAY_IFD TISDO_DO_IOBDELAY_NONE D input to DO output pin (IOBDELAY = IFD) D input to DO output pin (IOBDELAY = NONE) D input to DO output pin (IOBDELAY = BOTH, IOBDELAY_TYPE = DEFAULT) D input to DO output pin(1) (IOBDELAY = BOTH, IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) D input to DO output pin (IOBDELAY = IBUF, IOBDELAY_TYPE = DEFAULT) D input to DO output pin(1) (IOBDELAY = IBUF, IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 0.17 0.17 6.00 0.74 6.00 0.74 0.20 0.20 6.91 0.79 6.91 0.79 0.24 0.24 7.96 0.99 7.96 0.99 ns ns ns ns ns ns CLKDIV to out at Q pin 0.59 0.71 0.85 ns 0.24 -0.11 6.64 -6.51 0.81 -0.68 0.24 -0.11 6.64 -6.51 0.81 -0.68 0.28 -0.11 7.63 -6.51 0.87 -0.68 0.28 -0.11 7.63 -6.51 0.87 -0.68 0.34 -0.11 8.84 -6.51 1.08 -0.68 0.34 -0.11 8.84 -6.51 1.08 -0.68 ns BITSLIP pin Setup/Hold with respect to CLKDIV CE pin Setup/Hold with respect to CLK (for CE1) CE pin Setup/Hold with respect to CLKDIV (for CE2) DLYCE pin Setup/Hold with respect to CLKDIV DLYINC pin Setup/Hold with respect to CLKDIV DLYRST pin Setup/Hold with respect to CLKDIV SR pin Setup with respect to CLKDIV 0.28 -0.20 0.48 -0.37 0.11 -0.04 0.16 0.11 0.01 0.36 -0.03 0.37 0.64 0.34 -0.16 0.57 -0.30 0.14 -0.03 0.19 0.13 0.01 0.43 -0.02 0.45 0.77 0.40 -0.13 0.69 -0.25 0.16 -0.02 0.23 0.16 0.01 0.51 -0.02 0.54 0.92 ns ns ns ns ns ns ns
Description
-12
-11
-10
Units
ns
ns
ns
ns
ns
TISDO_DO_IOBDELAY_BOTH
TISDO_DO_IOBDELAY_IBUF
Notes: 1. Recorded at 0 tap value. Refer to Timing Report for other values. 2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE / TISCKC_CE in TRCE report.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 28
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Input Delay Switching Characteristics
Table 35: Input Delay Switching Characteristics Speed Grade Symbol
TIDELAYRESOLUTION TIDELAYTOTAL_ERR TIDELAYCTRLCO_RDY FIDELAYCTRL_REF
IDELAYCTRL_REF_PRECISION (3)
Description
IDELAY Chain Delay Resolution Cumulative delay at a given tap (2) Reset to Ready for IDELAYCTRL (Maximum) REFCLK frequency REFCLK precision Minimum Reset pulse width Pattern dependent period jitter in delay chain for clock pattern Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)
-12
75
-11
75 [(tap -1) x 75 +34] 0.07[(tap -1) x 75 +34]
-10
75
Units
ps ps s
3.00 200 10 50.0 0 10 2
3.00 200 10 50.0 0 10 2
3.00 200 10 50.0 0 10 2
MHz MHz
ns
TIDELAYCTRL_RPW
Note (4) Note (4)
TIDELAYPAT_JIT
Notes: 1. Refer to Xilinx Application Note XAPP707 for details on IDELAY timing characteristics. 2. This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps. 3. See the "REFCLK - Reference Clock" section (specific to IDELAYCTRL) in the Virtex-4 FPGA User Guide: Chapter 7, SelectIO Logic Resources. 4. Units in ps peak-to-peak per tap.
Output Serializer/Deserializer Switching Characteristics
Table 36: OSERDES Switching Characteristics Speed Grade Symbol
Setup/Hold TOSDCK_D / TOSCKD_D TOSDCK_T / TOSCKD_T(1) TOSDCK_T2 / TOSCKD_T2(1) TOSCCK_OCE / TOSCKC_OCE TOSCCK_S TOSCCK_TCE / TOSCKC_TCE Sequential Delays TOSCKO_OQ TOSCKO_TQ Combinatorial TOSDO_TTQ TOSCO_OQ TOSCO_TQ T input to TQ Out Asynchronous Reset to OQ Asynchronous Reset to TQ 0.56 1.14 1.14 0.65 1.37 1.37 0.76 1.64 1.64 ns ns ns Clock to out from CLK to OQ Clock to out from CLK to TQ 0.41 0.41 0.49 0.49 0.59 0.59 ns ns D input Setup/Hold with respect to CLKDIV T input Setup/Hold with respect to CLK T input Setup/Hold with respect to CLKDIV OCE input Setup/Hold with respect to CLK SR (Reset) input Setup with respect to CLKDIV TCE input Setup/Hold with respect to CLK 0.35 -0.05 0.43 -0.16 0.35 -0.05 0.45 0.01 0.67 0.45 0.01 0.42 -0.04 0.52 -0.16 0.42 -0.04 0.53 0.02 0.80 0.53 0.02 0.50 -0.03 0.62 -0.16 0.50 -0.03 0.64 0.03 0.96 0.64 0.03 ns ns ns ns ns ns
Description
-12
-11
-10
Units
Notes: 1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T / TOSCKD_T in TRCE report.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 29
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics
Table 37: CLB Switching Characteristics Speed Grade -12 Symbol
Combinatorial Delays TILO TIF5 TIF5X TIF6Y TINAFX TINBFX TBXX TBYY TBXCY TBYCY TBYP TOPCYF TOPCYG Sequential Delays TCKO TCKLO FF Clock CLK to XQ/YQ outputs Latch Clock CLK to XQ/YQ outputs 0.28 0.37 0.28 0.36 0.31 0.41 0.36 0.48 ns, Max ns, Max 4-input function: F/G inputs to X/Y outputs 5-input function: F/G inputs to F5 output 5-input function: F/G inputs to X output FXINA or FXINB inputs to YMUX output FXINA input to FX output via MUXFX FXINB input to FX output via MUXFX BX input to XMUX output BY input to YMUX output BX input to COUT output - Getting into carry chain(3) 0.15 0.36 0.44 0.30 0.21 0.21 0.59 0.43 0.60 0.49 0.07 chain(3) chain(3) 0.45 0.44 0.15 0.35 0.43 0.30 0.21 0.20 0.58 0.43 0.59 0.48 0.07 0.44 0.43 0.17 0.40 0.49 0.34 0.23 0.23 0.65 0.48 0.66 0.54 0.08 0.50 0.48 0.20 0.46 0.57 0.39 0.27 0.26 0.76 0.56 0.78 0.63 0.09 0.58 0.57 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
-11
-10 Units
Description
XC4VFX(2)
XC4VLX/SX
ALL DEVICES
BY input to COUT output - Getting into carry chain(3) CIN input to COUT output - Carry chain delay(3) F input to COUT output - Getting out from carry G input to COUT output - Getting out from carry
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TDICK / TCKDI TCECK / TCKCE TFXCK / TCKFX TSRCK / TCKSR TCINCK / TCKCIN Set/Reset TRPW TRQ FTOG Minimum Pulse Width, SR/BY inputs Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) Toggle Frequency (MHz) (for export control) 0.54 1.05 1181 0.53 1.03 1205 0.59 1.15 1205(4) 0.70 1.35 1028 ns, Min ns, Max MHz BX/BY inputs CE input FXINA/FXINB inputs SR/BY inputs (synchronous) CIN Data Inputs (DI) - Getting out from carry chain(3) 0.36 -0.09 0.58 -0.16 0.42 -0.14 1.04 -0.74 0.52 -0.23 0.36 -0.09 0.57 -0.16 0.41 -0.14 1.02 -0.73 0.51 -0.23 0.40 -0.09 0.64 -0.16 0.46 -0.14 1.15 -0.73 0.57 -0.23 0.47 -0.09 0.75 -0.16 0.54 -0.14 1.35 -0.73 0.67 -0.23 ns, Min ns, Min ns, Min ns, Min ns, Min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. 2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent 4VLX/SX -12 column. 3. These items are of interest for Carry Chain applications. 4. XC4VFX -11 devices are 1181 MHz.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 30
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
)
Table 38: CLB Distributed RAM Switching Characteristics Speed Grade -12 Symbol
Sequential Delays TSHCKO TSHCKOF5 Clock CLK to X outputs (WE active)(3) Clock CLK to F5 output (WE active) 1.61 1.53 1.26 -0.90 0.88 -0.37 1.10 -0.48 0.53 0.55 0.76 1.58 1.50 1.23 -0.88 0.86 -0.37 1.08 -0.47 0.52 0.54 0.74 1.77 1.69 1.46 -0.88 0.97 -0.34 1.21 -0.47 0.59 0.60 0.84 2.08 1.98 1.80 -0.88 1.13 -0.29 1.42 -0.47 0.69 0.70 0.98 ns, Max ns, Max
-11
-10 Units
Description
XC4VFX(2)
XC4VLX/SX
ALL DEVICES
Setup and Hold Times Before/After Clock CLK TDS / TDH TAS / TAH TWS / TWH Clock CLK TWPH TWPL TWC Minimum Pulse Width, High Minimum Pulse Width, Low Minimum clock period to meet address write cycle time ns, Min ns, Min ns, Min BX/BY data inputs (DI) F/G address inputs WE input (SR) ns, Min ns, Min ns, Min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. 2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent XC4VLX/SX -12 column. 3. TSHCKO also represents the CLK to XMUX output. Refer to TRCE report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)
)
Table 39: CLB Shift Register Switching Characteristics Speed Grade -12 Symbol
Sequential Delays TREG TREGXB TREGYB TCKSH TREGF5 Clock CLK to X/Y outputs Clock CLK to XB output via MC15 LUT output Clock CLK to YB output via MC15 LUT output Clock CLK to Shiftout Clock CLK to F5 output 2.12 1.83 1.84 1.70 2.05 0.87 -0.76 1.28 -1.12 0.53 0.55 2.08 1.73 1.74 1.60 2.01 0.85 -0.76 1.25 -1.11 0.52 0.54 2.19 1.90 1.92 1.76 2.11 0.96 -0.70 1.45 -1.11 0.59 0.60 2.19 1.84 1.85 1.70 2.11 0.96 -0.70 1.45 -1.11 0.59 0.60 2.57 2.16 2.17 1.99 2.47 1.12 -0.62 1.75 -1.11 0.69 0.70 ns, Max ns, Max ns, Max ns, Max ns, Max
-11
XC4VFX(3) XC4VLX/SX
-10
ALL
Description
XC4VFX(2)
XC4VLX/SX
Units
Setup and Hold Times Before/After Clock CLK TWS / TWH TDS / TDH Clock CLK TWPH TWPL Minimum Pulse Width, High Minimum Pulse Width, Low ns, Min ns, Min WE input (SR) BX/BY data inputs (DI) ns, Min ns, Min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. 2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent XC4VLX/SX -12 column. 3. The values in this column apply to all XC4VFX -11 parts.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 31
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 40: Block RAM Switching Characteristics Speed Grade Symbol
Sequential Delays Clock CLK to DOUT output (without output register)(2) TRCKO_DORA Clock CLK to DOUT output with ECC (without output register) Clock CLK to DOUT output (with output register)(3) TRCKO_DOA Clock CLK to DOUT output with ECC (with output register) 1.65 3.00 0.72 2.00 1.83 3.33 0.80 2.20 2.10 3.83 0.92 2.50 ns, Max ns, Max ns, Min ns, Max
Description
-12
-11
-10
Units
Setup and Hold Times Before Clock CLK TRCCK_ADDR / TRCKC_ADDR TRDCK_DI / TRCKD_DI TRCCK_EN / TRCKC_EN TRCCK_REGCE /TRCKC_REGCE TRCCK_SSR / TRCKC_SSR TRCCK_WE / TRCKC_WE Maximum Frequency FMAX FMAX CLK-to-CLK Write first and no change mode Read first mode Read first mode 500.00 500.00 500.00 450.45 450.45 450.45 400.00 400.00 400.00 MHz MHz MHz ADDR inputs DIN inputs(4) EN input(5) CE input of output register RST input WEN input 0.34 0.26 0.18 0.26 0.41 0.26 0.25 0.26 0.25 0.26 0.59 0.26 0.37 0.28 0.20 0.28 0.45 0.28 0.27 0.28 0.27 0.28 0.65 0.28 0.43 0.33 0.23 0.33 0.52 0.33 0.32 0.33 0.32 0.33 0.75 0.33 ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. 2. TRCKO_DORA includes TRCKO_DOWA, TRCKO_DOPAR, and TRCKO_DOPAW as well as the B port equivalent timing parameters. 3. TRCKO_DOA includes TRCKO_DOPA as well as the B port equivalent timing parameters. 4. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B. 5. Xilinx block RAMs do not have asynchronous inputs on an enabled port address. During the time that a port is enabled, its addresses must be stable during the specified set-up time. Do not create an asynchronous input on an enabled port address.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 32
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 41: FIFO Switching Characteristics Speed Grade Symbol
Sequential Delays TFCKO_DO TFCKO_FLAGS TFCKO_POINTERS Clock CLK to DO output (2) Clock CLK to FIFO flags outputs (3) Clock CLK to FIFO pointer outputs (4) 0.72 0.93 1.16 0.80 1.04 1.29 0.92 1.19 1.48 ns, Max ns, Max ns, Max
Description
-12
-11
-10
Units
Setup and Hold Times Before Clock CLK TFDCK_DI / TFCKD_DI TFCCK_EN / TFCKC_EN Reset Delays TFCO_FLAGS Maximum Frequency FMAX FIFO in all modes 500.00 450.45 400.00 MHz Reset RST to FLAGS (7) 1.32 1.46 1.68 ns, Max DI input (5) Enable inputs (6) 0.18 0.26 0.66 0.26 0.20 0.28 0.73 0.28 0.23 0.33 0.84 0.33 ns, Min ns, Min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. 2. TFCKO_DO includes parity output (TFCKO_DOP). 3. TFCKO_FLAGS includes the following parameters: TFCKO_AEMPTY, TFCKO_AFULL, TFCKO_EMPTY, TFCKO_FULL, TFCKO_RDERR, TFCKO_WRERR. 4. TFCKO_POINTERS includes both TFCKO_RDCOUNT and TFCKO_WRCOUNT. 5. TFDCK_DI includes parity inputs (TFDCK_DIP). 6. TFCCK_EN includes both WRITE and READ enable. 7. TFCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT and WRCOUNT.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 33
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
XtremeDSPTM Switching Characteristics
Table 42: XtremeDSP Switching Characteristics Speed Grade Symbol
Setup and Hold of CE Pins TDSPCCK_CE / TDSPCKC_CE TDSPCCK_RST / TDSPCKC_RST Setup and Hold Times of Data TDSPDCK_{AA, BB, CC} / TDSPCKD_{AA, BB, CC} TDSPDCK_{AM, BM} / TDSPCKD_{AM, BM} Sequential Delays TDSPCKO_PP TDSPCKO_PM Combinatorial TDSPDO_{AP, BP}L Maximum Frequency FMAX From {A, B} register to P register (LEGACY_MODE = MULT18X18) Fully Pipelined 317.46 500.00 285.71 450.05 253.94 400.00 MHz MHz {A, B} input to P output (LEGACY_MODE = MULT18X18) 3.53 3.92 4.41 ns Clock to out from P register to P output Clock to out from M register to P output 0.64 2.38 0.71 2.65 0.79 2.98 ns ns Setup/Hold of {A, B, C} input to {A, B, C} register Setup/Hold of {A, B} input to M register 0.25 0.23 1.82 0.00 0.28 0.26 2.03 0.00 0.32 0.29 2.28 0.00 ns ns Setup/Hold of all CE inputs of the DSP48 slice Setup/Hold of all RST inputs of the DSP48 slice 0.39 0.09 0.32 0.09 0.43 0.10 0.36 0.10 0.49 0.12 0.40 0.12 ns ns
Description
-12
-11
-10
Units
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 34
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 43: Configuration Switching Characteristics Speed Grade Symbol
Power-up Timing Characteristics TCONFIG(1,2) TPL TPOR TICCK TPROGRAM Maximum time to configure device after VCCINT has been applied. Program Latency Power-on-Reset CCLK (output) delay Program Pulse Width 10 0.5 10 0.5 10 0.5 minutes s/frame, Max ms, Max ns, Min ns, Min
Description
-12
-11
-10
Units
TPL + 10 TPL + 10 TPL + 10 500 300 500 300 500 300
Master/Slave Serial Mode Programming Switching TDCC / TCCD TDSCK / TSCKD TCCO TCCH TCCL FCC_SERIAL FMAX_SLAVE / FMAX_ICAP FMCCTOL SelectMAP Mode Programming Switching TSMDCC / TSMCCD TSMCSCC / TSMCCCS TSMCCW / TSMWCC TSMCKBY FCC_SELECTMAP FMAX_SELECTMAP FMAX_READBACK FMCCTOL TSMCO SelectMAP Data Setup/Hold CS_B Setup/Hold RDWR_B Setup/Hold BUSY Propagation Delay Maximum Frequency, master mode with respect to nominal CCLK. Maximum Configuration Frequency, slave mode external CCLK Maximum Readback Frequency Frequency Tolerance, master mode with respect to nominal CCLK. SelectMAP Readback Clock-to-Out 2.0 0.0 1.0 0.5 6.0 1.0 8.0 100 100 80 50 8.0 2.0 0.0 1.0 0.5 6.0 1.0 8.0 100 100 80 50 8.0 2.0 0.0 1.0 0.5 6.0 1.0 8.0 100 100 80 50 8.0 ns, Min ns, Min ns, Min ns, Max MHz, Max MHz, Max MHz, Max % ns, Max DIN Setup/Hold, slave mode DIN Setup/Hold, master mode DOUT High Time Low Time Maximum Frequency, master mode with respect to nominal CCLK. Maximum Frequency, slave mode external CCLK Frequency Tolerance, master mode with respect to nominal CCLK. 0.5 1.0 0.5 1.0 7.5 2.0 2.0 100 100 50 0.5 1.0 0.5 1.0 7.5 2.0 2.0 100 100 50 0.5 1.0 0.5 1.0 7.5 2.0 2.0 100 100 50 ns, Min ns, Min ns, Max ns, Min ns, Min MHz, Max MHz, Max %
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 35
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 43: Configuration Switching Characteristics (Continued) Speed Grade Symbol
Boundary-Scan Port Timing Specifications TTAPTCK TTCKTAP TTCKTDO FTCK FTCKB TMS and TDI Setup time before TCK TMS and TDI Hold time after TCK TCK falling edge to TDO output valid Maximum configuration TCK clock frequency Maximum Boundary-Scan TCK clock frequency 1.0 2.0 6.0 66 50 1.0 2.0 6.0 66 50 1.0 2.0 6.0 66 50 ns, Min ns, Min ns, Max MHz, Max MHz, Max
Description
-12
-11
-10
Units
Dynamic Reconfiguration Port (DRP) for DCM CLKIN_FREQ_DLL_HF_MS_MAX TDMCCK_DADDR/TDMCKC_DADDR TDMCCK_DI/TDMCKC_DI TDMCCK_DEN/TDMCKC_DEN TDMCCK_DWE/TDMCKC_DWE TDMCKO_DO TDMCKO_DRDY Maximum frequency for DCLK DADDR Setup/Hold time DI Setup/Hold time DEN Setup/Hold time DWE Setup/Hold time CLK to out of DO(2) CLK to out of DRDY 500 0.54 0.00 0.54 0.00 0.58 0.00 0.58 0.00 0 0.68 450 0.63 0.00 0.63 0.00 0.58 0.00 0.58 0.00 0 0.80 400 0.72 0.00 0.72 0.00 0.58 0.00 0.58 0.00 0 0.92 MHz, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Notes: 1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. 2. DO holds until the next DRP operation.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 36
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 44: Global Clock Switching Characteristics (Including BUFGCTRL) Speed Grade Symbol
TBCCCK_CE / TBCCKC_CE(1) TBCCCK_S / TBCCKC_S(1) TBCCKO_O Maximum Frequency FMAX Global clock tree 500 450 400 MHz CE pins Setup/Hold S pins Setup/Hold BUFGCTRL delay
Description
-12
0.27 0.00 0.27 0.00 0.70
-11
0.31 0.00 0.31 0.00 0.77
-10
0.35 0.00 0.35 0.00 0.90
Units
ns ns ns
Notes: 1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.
DCM and PMCD Switching Characteristics
Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode Speed Grade Symbol
Outputs Clocks (Low Frequency Mode) CLKOUT_FREQ_1X_LF_MS_MIN CLKOUT_FREQ_1X_LF_MS_MAX CLKOUT_FREQ_2X_LF_MS_MIN CLKOUT_FREQ_2X_LF_MS_MAX CLKOUT_FREQ_DV_LF_MS_MIN CLKOUT_FREQ_DV_LF_MS_MAX CLKOUT_FREQ_FX_LF_MS_MIN CLKOUT_FREQ_FX_LF_MS_MAX Input Clocks (Low Frequency Mode) CLKIN_FREQ_DLL_LF_MS_MIN CLKIN_FREQ_DLL_LF_MS_MAX CLKIN_FREQ_FX_LF_MS_MIN CLKIN_FREQ_FX_LF_MS_MAX PSCLK_FREQ_LF_MS_MIN PSCLK_FREQ_LF_MS_MAX Outputs Clocks (High Frequency Mode) CLKOUT_FREQ_1X_HF_MS_MIN CLKOUT_FREQ_1X_HF_MS_MAX CLKOUT_FREQ_2X_HF_MS_MIN CLKOUT_FREQ_2X_HF_MS_MAX CLKOUT_FREQ_DV_HF_MS_MIN CLKOUT_FREQ_DV_HF_MS_MAX CLK0, CLK90, CLK180, CLK270 150 500 300 500 9.4 333 150 450 300 450 9.4 300 150 400 300 400 9.4 267 MHz MHz MHz MHz MHz MHz CLKIN (using DLL outputs)(1,3,4,5,6) CLKIN (using DFS outputs only)(2,3,4) 32 150 1 210 1 500 32 150 1 210 1 450 32 150 1 210 1 400 MHz MHz MHz MHz KHz MHz CLK0, CLK90, CLK180, CLK270 32 150 64 300 2 100 32 210 32 150 64 300 2 100 32 210 32 150 64 300 2 100 32 210 MHz MHz MHz MHz MHz MHz MHz MHz
Description
-12
-11
-10
Units
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
PSCLK
CLK2X, CLK2X180
CLKDV
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 37
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Continued) Speed Grade Symbol
CLKOUT_FREQ_FX_HF_MS_MIN CLKOUT_FREQ_FX_HF_MS_MAX Input Clocks (High Frequency Mode) CLKIN_FREQ_DLL_HF_MS_MIN CLKIN_FREQ_DLL_HF_MS_MAX CLKIN_FREQ_FX_HF_MS_MIN CLKIN_FREQ_FX_HF_MS_MAX PSCLK_FREQ_HF_MS_MIN PSCLK_FREQ_HF_MS_MAX CLKIN (using DLL outputs)(1,3,4,5,6) CLKIN (using DFS outputs only)(2,3,4) 150 500 50 350 1 500 150 450 50 315 1 450 150 400 50 300 1 400 MHz MHz MHz MHz KHz MHz
Description
CLKFX, CLKFX180
-12
210 350
-11
210 315
-10
210 300
Units
MHz MHz
PSCLK
Notes: 1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. 4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45). 5. The DCM must be reset if the clock input clock stops for more than 100 ms. 6. These values also apply when using both DLL and DFS outputs.
Table 46: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode Speed Grade Symbol
Outputs Clocks (Low Frequency Mode) CLKOUT_FREQ_1X_LF_MR_MIN CLKOUT_FREQ_1X_LF_MR_MAX CLKOUT_FREQ_2X_LF_MR_MIN CLKOUT_FREQ_2X_LF_MR_MAX CLKOUT_FREQ_DV_LF_MR_MIN CLKOUT_FREQ_DV_LF_MR_MAX CLKOUT_FREQ_FX_LF_MR_MIN CLKOUT_FREQ_FX_LF_MR_MAX Input Clocks (Low Frequency Mode) CLKIN_FREQ_DLL_LF_MR_MIN CLKIN_FREQ_DLL_LF_MR_MAX CLKIN_FREQ_FX_LF_MR_MIN CLKIN_FREQ_FX_LF_MR_MAX PSCLK_FREQ_LF_MR_MIN PSCLK_FREQ_LF_MR_MAX CLKIN (using DLL outputs)(1,3,4,5,6) CLKIN (using DFS outputs only)(2,3,4) 19 40 1 35 1 262.50 19 36 1 32 1 236.30 19 32 1 28 1 210.00 MHz MHz MHz MHz KHz MHz CLK0, CLK90, CLK180, CLK270 19 40 38 80 1.2 26.7 19 40 19 36 38 72 1.2 24 19 36 19 32 38 64 1.2 21.3 19 32 MHz MHz MHz MHz MHz MHz MHz MHz
Description
-12
-11
-10
Units
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
PSCLK
Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. 4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45). 5. The DCM must be reset if the clock input clock stops for more than 100 ms. 6. These values also apply when using both DLL and DFS outputs.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 38
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 47: Input Clock Tolerances Symbol
Duty Cycle Input Tolerance (in %) CLKIN_PSCLK_PULSE_RANGE_1 CLKIN_PSCLK_PULSE_RANGE_1_50 CLKIN_PSCLK_PULSE_RANGE_50_100 CLKIN_PSCLK_PULSE_RANGE_100_200 CLKIN_PSCLK_PULSE_RANGE_200_400 CLKIN_PSCLK_PULSE_RANGE_400 PSCLK and CLKIN PSCLK only < 1 MHz 1 - 50 MHz (1) 50 - 100 MHz (1) 25 - 75 25 - 75 30 - 70 40 - 60 45 - 55 45 - 55 % % % % % %
Description
Frequency Range
Value
Units
100 - 200 MHz (1) 200 - 400 MHz (1) > 400 MHz Speed Grade -12 -11
-10
Input Clock Cycle-Cycle Jitter (Low Frequency Mode) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_FX_LF CLKIN (using DLL outputs)(2,5,6) CLKIN (using DFS outputs)(3) 300 300 300 300 345 345 ps ps
Input Clock Cycle-Cycle Jitter (High Frequency Mode) CLKIN_CYC_JITT_DLL_HF CLKIN_CYC_JITT_FX_HF Input Clock Period Jitter (Low Frequency Mode) CLKIN_PER_JITT_DLL_LF CLKIN_PER_JITT_FX_LF Input Clock Period Jitter (High Frequency Mode) CLKIN_PER_JITT_DLL_HF CLKIN_PER_JITT_FX_HF Feedback Clock Path Delay Variation CLKFB_DELAY_VAR_EXT CLKFB off-chip feedback 1.0 1.0 1.15 ns CLKIN (using DLL outputs)(2,5,6) CLKIN (using DFS outputs)(3) 1.0 1.0 1.0 1.0 1.15 1.15 ns ns CLKIN (using DLL outputs)(2,5,6) CLKIN (using DFS outputs)(3) 1.0 1.0 1.0 1.0 1.15 1.15 ns ns CLKIN (using DLL outputs)(2,5,6) CLKIN (using DFS outputs)(3) 150 150 150 150 173 173 ps ps
Notes: 1. For boundary frequencies, use the more restrictive specifications. 2. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 3. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 4. If both DLL and DFS outputs are used, follow the more restrictive specifications. 5. The DCM must be reset if the clock input clock stops for more than 100 ms. 6. These values also apply when using both DLL and DFS outputs.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 39
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Output Clock Jitter
Table 48: Output Clock Jitter Speed Grade Description
Clock Synthesis Period Jitter CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180 CLKOUT_PER_JITT_0 CLKOUT_PER_JITT_90 CLKOUT_PER_JITT_180 CLKOUT_PER_JITT_270 CLKOUT_PER_JITT_2X CLKOUT_PER_JITT_DV1 CLKOUT_PER_JITT_DV2 CLKOUT_PER_JITT_FX 100 150 150 150 200 150 300 Note (2) 100 150 150 150 200 150 300 Note (2) 100 150 150 150 200 150 300 Note (2) ps ps ps ps ps ps ps ps
Symbol
Constraints
-12
-11
-10
Units
Notes: 1. PMCD outputs are not included in this table because they do not introduce jitter. 2. Values for this parameter are available from the architecture wizard.
Output Clock Phase Alignment
Table 49: Output Clock Phase Alignment Speed Grade Description
Phase Offset Between CLKIN and CLKFB CLKIN / CLKFB CLKIN_CLKFB_PHASE 120 120 120 ps
Symbol
Constraints
-12
-11
-10
Units
Phase Offset Between Any DCM Outputs All CLK outputs Duty Cycle Precision DLL outputs(1) DFS outputs(2) CLKOUT_DUTY_CYCLE_DLL(3,4) CLKOUT_DUTY_CYCLE_FX(4) 150 200 150 200 150 200 ps ps CLKOUT_PHASE 140 140 140 ps
Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION=TRUE. 4. The measured value includes the duty cycle distortion of the global clock tree.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 40
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 50: Miscellaneous Timing Parameters Speed Grade Symbol
Time Required to Achieve LOCK T_LOCK_DLL_240 T_LOCK_DLL_120_240 T_LOCK_DLL_60_120 T_LOCK_DLL_50_60 T_LOCK_DLL_40_50 T_LOCK_DLL_30_40 T_LOCK_DLL_24_30 T_LOCK_DLL_30 T_LOCK_FX_MAX T_LOCK_DLL_FINE_SHIFT Fine Phase Shifting FINE_SHIFT_RANGE_MS FINE_SHIFT_RANGE_MR Delay Lines DCM_TAP_MS_MIN DCM_TAP_MS_MAX DCM_TAP_MR_MIN DCM_TAP_MR_MAX Input Signal Requirements DCM_RESET(4) Minimum duration that RST must be held asserted Maximum duration that RST can be held asserted.(5) Maximum duration that CLKIN and CLKFB can be stopped(6,7). Tap delay resolution (Min) in maximum speed mode Tap delay resolution (Max) in maximum speed mode Tap delay resolution (Min) in maximum range mode Tap delay resolution (Max) in maximum range mode 5 40 10 60 5 40 10 60 5 40 10 60 ps ps ps ps Absolute shifting range in maximum speed mode Absolute shifting range in maximum range mode 7 10 7 10 7 10 ns ns DLL output - Frequency range > 240 MHz (2) DLL output - Frequency range 120 - 240 MHz (1,2) DLL output - Frequency range 60 - 120 MHz (1,2) DLL output - Frequency range 50 - 60 MHz(1,2)
(1,2)
Description
-12
-11
-10
Units
20 63 225 325 500 900 1250 1250 10 2
20 63 225 325 500 900 1250 1250 10 2
20 63 225 325 500 900 1250 1250 10 2
s s s s s s s s ms
DLL output - Frequency range 40 - 50 MHz
DLL output - Frequency range 30 - 40 MHz (1,2) DLL output - Frequency range 24 - 30 MHz(1,2) DLL output - Frequency range < 30 MHz (2) DFS outputs(3)
Multiplication factor for DLL lock time with Fine Shift
200 10 100
200 10 100
200 10 100
ms sec ms
DCM_INPUT_CLOCK_STOP
Notes: 1. For boundary frequencies, choose the higher delay. 2. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 3. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 4. CLKIN must be present and stable during the DCM_RESET. 5. This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in Answer Record 21127 for support of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement. 6. For production step 1 LX and SX devices, use the design solutions described in Answer Record 21127 for support of longer durations of stopped clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support longer durations of stopped clocks. 7. For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 41
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 51: Frequency Synthesis Attribute
CLKFX_MULTIPLY CLKFX_DIVIDE
Min
2 1
Max
32 32
Table 52: DCM Switching Characteristics Symbol
TDMCCK_PSEN / TDMCKC_PSEN TDMCCK_PSINCDEC / TDMCKC_PSINCDEC TDMCKO_PSDONE PSEN Setup/Hold PSINCDEC Setup/Hold Clock to out of PSDONE
Description
Speed Grade -12
0.93 0.00 0.93 0.00 0.60
-11
0.93 0.00 0.93 0.00 0.60
-10
1.07 0.00 1.07 0.00 0.69
Units
ns ns ns
Table 53: PMCD Switching Characteristic Symbol
TPMCCCK_REL / TPMCCKC_REL TPMCCO_CLK{A1,B,C,D} TPMCCKO_CLK{A1,B,C,D} PMCD_CLK_SKEW CLKIN_FREQ_PMCD_CLKA_MAX (1) CLKIN_PSCLK_PULSE_RANGE PMCD_REL_HIGH_PULSE_MIN PMCD_RST_HIGH_PULSE_MIN
Description
REL Setup/Hold for all outputs RST assertion to clock output deassertion Max clock propagation delay of PMCD for all outputs Max phase between all outputs assuming all inputs Max input/output frequency Max duty cycle input tolerance (same as DCM) Min pulse width for REL Min pulse width for RST
Speed Grade -12
0.60 0.00 4.00 4.60 150 500
-11
0.60 0.00 4.00 4.60 150 450 Note (2)
-10
0.60 0.00 4.50 5.20 150 400
Units
ns ns ns ps MHz
1.11 1.11
1.11 1.11
1.25 1.25
ns ns
Notes: 1. There is no minimum frequency for PMCD. 2. Refer to Table 47 parameter: CLKIN_PSCLK_PULSE_RANGE.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 42
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
System-Synchronous Switching Characteristics
Virtex-4 FPGA Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 54. Values are expressed in nanoseconds unless otherwise noted. Table 54: Global Clock Input to Output Delay for LVCMOS25 Standard, 12 mA, Fast Slew Rate, with DCM Symbol Description Device Speed Grade -12 -11 -10 Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM. TICKOFDCM Global Clock and OFF with DCM XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 2.43 2.60 2.54 2.69 2.88 2.94 2.94 N/A 2.65 2.81 2.83 2.43 2.54 2.87 2.92 3.16 N/A 2.81 2.95 2.91 3.05 3.27 3.33 3.35 3.51 2.99 3.18 3.20 2.78 2.88 3.25 3.31 3.58 3.79 3.25 3.36 3.32 3.45 3.72 3.79 3.82 4.02 3.39 3.60 3.62 3.18 3.26 3.67 3.77 4.06 4.30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 43
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 55: Global Clock Input to Output Delay for LVCMOS25 Standard, 12 mA, Fast Slew Rate, without DCM Symbol Description Device Speed Grade -12 -11 -10 Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12 mA, Fast Slew Rate, without DCM. TICKOF Global Clock and OFF without DCM XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 6.42 6.50 6.70 6.86 6.98 7.23 7.46 N/A 6.69 6.75 7.10 6.41 6.60 6.97 6.98 7.46 N/A 7.22 7.32 7.54 7.72 7.85 8.15 8.40 8.79 7.52 7.59 7.99 7.21 7.42 7.84 7.86 8.40 8.80 8.14 8.25 8.50 8.70 8.85 9.18 9.46 9.88 8.47 8.56 9.00 8.13 8.37 8.83 8.85 9.45 9.90 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 44
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Virtex-4 FPGA Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 56. Values are expressed in nanoseconds unless otherwise noted. Table 56: Global Clock Setup and Hold for LVCMOS25 Standard, with DCM Symbol Description Device Speed Grade -12 -11 -10 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCM / TPHDCM No Delay Global Clock and IFF(2) with DCM XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 1.35 -0.72 1.28 -0.58 1.25 -0.55 1.25 -0.43 1.22 -0.26 1.27 -0.20 1.54 -0.20 N/A 1.25 -0.50 1.21 -0.41 1.25 -0.23 1.35 -0.71 1.25 -0.52 1.23 -0.18 1.17 -0.06 1.21 0.11 N/A 1.52 -0.67 1.50 -0.57 1.44 -0.50 1.47 -0.40 1.42 -0.21 1.48 -0.14 1.79 -0.13 1.90 0.03 1.47 -0.48 1.43 -0.38 1.47 -0.18 1.55 -0.69 1.48 -0.51 1.45 -0.13 1.37 0.01 1.42 0.20 1.68 0.21 1.54 -0.62 1.58 -0.55 1.50 -0.46 1.55 -0.36 1.49 -0.15 1.56 -0.08 1.89 -0.05 2.00 0.15 1.55 -0.48 1.50 -0.34 1.55 -0.13 1.61 -0.69 1.56 -0.51 1.52 -0.08 1.44 0.09 1.49 0.31 1.76 0.31 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. These measurements include: CLK0 DCM jitter IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 45
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 57: Global Clock Setup and Hold for LVCMOS25 Standard, with DCM in Source-Synchronous Mode Speed Grade Symbol Description Device
-12 -11 -10
Units
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Switching Characteristics(1,2), page 19.
TPSDCM_0 / TPHDCM_0
No Delay Global Clock and IFF (2) with DCM in Source-Synchronous Mode
XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140
-0.33 0.73 -0.29 0.86 -0.37 0.90 -0.32 1.02 -0.38 1.18 -0.31 1.24 -0.31 1.50 N/A -0.32 0.95 -0.37 1.04 -0.32 1.22 -0.26 0.73 -0.31 0.92 -0.35 1.26 -0.43 1.39 -0.38 1.55 N/A
-0.33 0.88 -0.29 0.97 -0.37 1.04 -0.32 1.15 -0.38 1.34 -0.31 1.41 -0.31 1.69 -0.31 1.97 -0.32 1.07 -0.37 1.17 -0.32 1.36 -0.26 0.86 -0.31 1.03 -0.35 1.41 -0.43 1.56 -0.38 1.75 -0.44 2.03
-0.33 1.03 -0.29 1.09 -0.37 1.19 -0.32 1.29 -0.38 1.50 -0.31 1.57 -0.31 1.89 -0.31 2.19 -0.32 1.17 -0.37 1.31 -0.32 1.52 -0.26 0.96 -0.31 1.14 -0.35 156 -0.43 1.74 -0.38 1.96 -0.44 2.25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CLK0 DCM jitter. Package skew is not included in these measurements. 2. IFF = Input Flip-Flop
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 46
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 58: Global Clock Setup and Hold for LVCMOS25 Standard, without DCM Symbol Description Device Speed Grade -12 -11 -10 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSFD / TPHFD Full Delay Global Clock and IFF(2) without DCM XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 1.82 0.11 1.79 0.20 2.06 0.13 2.39 0.04 2.36 0.16 4.85 -0.09 2.56 0.46 N/A 2.12 0.14 2.10 0.21 1.99 0.57 1.82 0.12 1.75 0.38 1.82 0.64 2.42 0.25 1.99 1.11 N/A 2.33 0.19 2.30 0.29 2.61 0.22 2.99 0.12 2.96 0.26 5.83 -0.09 3.21 0.59 3.57 0.64 2.68 0.23 2.66 0.30 2.53 0.71 2.33 0.20 2.26 0.49 2.34 0.78 3.03 0.35 2.21 1.31 2.80 1.26 2.74 0.39 2.70 0.50 3.06 0.44 3.50 0.34 3.47 0.49 6.76 -0.01 3.76 0.88 4.17 0.95 3.14 0.44 3.12 0.52 2.97 0.98 2.73 0.39 2.65 0.73 2.75 1.05 3.54 0.59 2.60 1.64 3.28 1.61 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 2. IFF = Input Flip-Flop or Latch. 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 47
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
ChipSyncTM Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-4 FPGA source-synchronous transmitter and receiver data-valid windows. Table 59: Duty Cycle Distortion and Clock-Tree Skew Symbol
TDCD_CLK TCKSKEW
Description
Global Clock Tree Duty Cycle Distortion (1) Global Clock Tree Skew
(2)
Device
All XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140
Speed Grade -12
150 50 90 140 140 200 270 270 N/A 50 90 140 50 60 90 140 200 N/A 100 50 50 250 710 300
-11
150 60 100 160 160 230 310 310 310 60 100 170 60 70 110 170 230 310 100 50 50 250 710 250
-10
150 60 110 180 180 260 350 350 350 70 120 190 70 70 120 190 260 350 100 50 50 250 645 250
Units
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps MHz MHz
TDCD_BUFIO
I/O clock tree duty cycle distortion I/O clock tree skew across one clock region
All All All All All All
TBUFIOSKEW TDCD_BUFR TBUFIO_MAX_FREQ TBUFR_MAX_FREQ
I/O clock tree skew across multiple clock regions Regional clock tree duty cycle distortion I/O clock tree MAX frequency Regional clock tree MAX frequency
Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. The TCKSKEW value represents the worst-case vertical clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 48
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 60: Package Skew Symbol
TPKGSKEW
Description
Package Skew(1)
Device
XC4VLX15
Package
SF363 FF668 SF363
Value
80 120 90 110 110 150 130 140 155 140 180 145 180 180 90 100 145 90 100 110 120 150 110 170 150 170 150
Units
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
XC4VLX25 FF668 FF668 XC4VLX40 FF1148 FF668 XC4VLX60 FF1148 XC4VLX80 XC4VLX100 FF1513 FF1148 XC4VLX160 FF1513 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 FF668 XC4VFX20 XC4VFX40 FF1152 FF672 XC4VFX60 FF1152 FF1152 XC4VFX100 FF1517 XC4VFX140 FF1517 FF672 FF672 FF1513 FF668 FF668 FF1148 SF363 FF1148 FF1148
Notes: 1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad to Ball (7.1 ps per mm). 2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 49
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 61: Sample Window Symbol
TSAMP TSAMP_BUFIO
Description
Sampling Error at Receiver Pins(1) Sampling Error at Receiver Pins using BUFIO(2)
Device
All All
Speed Grade -12
450 350
-11
500 400
-10
550 450
Units
ps ps
Notes: 1. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew. 2. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers' edges of operation. These measurements do not include package or clock tree skew.
Table 62: ChipSync Pin-to-Pin Setup/Hold and Clock-to-Out Symbol Description Speed Grade -12 -11 -10 Units
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO TPSCS / TPHCS Setup/Hold of I/O clock across multiple clock regions -0.45 0.97 -0.45 1.08 -0.44 1.17 ns
Pin-to-Pin Clock-to-Out Using BUFIO TICKOFCS Clock-to-Out of I/O clock across multiple clock regions 4.10 4.54 5.02 ns
Production Stepping
The Virtex-4 FPGA stepping identification system denotes the capability improvement of production released devices. By definition, devices from one stepping are functional supersets of previous devices. Bitstreams compiled for a device with an earlier stepping are guaranteed to operate correctly in subsequent device steppings. New device steppings can be shipped in place of earlier device steppings. Existing production designs are guaranteed on new device steppings. To take advantage of the capabilities of a newer device stepping, customers are able to order a new stepping version and compile a new bitstream. Production devices are marked with a stepping version, with the exception of some step 1 devices. Designs should be compiled with a CONFIG STEPPING parameter set to a specific stepping version. This parameter is set in the UCF file: CONFIG STEPPING = "#"; (where # is the stepping version) The default stepping level used by the ISE software is reported in the PAR report. Table 63 shows the JTAG ID code by step.
Table 63: JTAG ID Code by Step Device
XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140
Step 0
Step 1 3 9 3 2 or 3 3 2 or 3 0 or 3 0 or 3 2 2 2
Step 2 5 A 5 4 or 5 5 4 or 5 4 or 5 2 or 5 4 4 4
0 or 2 2 2 0 0 6 0 8 6 4
Notes: 1. Shaded cells represent devices not produced at that stepping.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 50
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Current Virtex-4 Production Devices
Table 64 summarizes the current production LX and SX device stepping. Table 64: Current LX and SX Production Devices LX/SX Device Stepping Example Ordering Code Device steppings shipped when ordered per Example Ordering Code Step 1 XC4VLX60-10FF672C Step 1 or Step 2 * Capability Improvements (1) The DFS macro is no longer needed Step 2 XC4VLX60-10FF672CS2 Step 2 * * * TCONFIG requirement is removed DCM_RESET requirement is removed DCM_INPUT_CLOCK_STOP requirement is removed by a macro (automatically inserted by ISE software)
CONFIG STEPPING parameter (must be set in UCF file) Minimum Software Required Minimum Speed Specification Required.
"1" ISE 7.1i SP4 1.58
"2" ISE 7.1i SP4 1.58
Notes: 1. See LX and SX Errata for details on LX and SX Step 1 and ES silicon.
Table 65 summarizes the current production FX device stepping. Table 65: Current FX Production Devices FX Device Stepping Example Ordering Code Device steppings shipped when ordered per Example Ordering Code Capability Improvements CONFIG STEPPING parameter (must be set in UCF file) Minimum Software Required Minimum Speed Specification Required "0" ISE 8.1i SP2 1.58 Step 0 XC4VFX60-10FF1152C Step 0 or Step 1 Step 1 XC4VFX60-10FF1152CS1 Step 1 See FX Errata for details "0" or "1" ISE 8.1i SP2 1.58
Notes: 1. Speed Specification v1.65 or later must be used for XC4VFX40 devices (all speed grades) and for XC4VFX100 (-12 speed grade only). In this case, these family members (and speed grades) are released to production before a speed specification is released with the correct label (Advance, Preliminary, or Production). These labeling discrepancies will be corrected in a subsequent speed specification release.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 51
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Revision History
The following table shows the revision history for this document. Date 08/02/04 09/09/04 01/18/05 02/01/05 Version 1.0 1.1 1.2 1.3 Revisions Initial Xilinx release. Printed Handbook version. Edits in Tables 12, 13, 18, 19, 20, 22, 26, 28, 37, and 38. Removed Table 39. Added parameters to Tables 4 and 5. Removed System Monitor and ADC parameters. Changed parameters in Tables 1, 2, 3, 7, and 11. Added Interface Performance Characteristics section. Added Switching Characteristics section and Table 14. Added parameters to the following tables: 4-6, 14, 16-30, 32-40, and 46. Changed the notes in Table 2. Added Set/Reset parameters to Table 32 and Table 33. Changed description in Table 35. Changed Set/Reset in Table 37. Changed PSCLK units in Table 45. Added parameters to Table 46. Changed DCM_TAP_MS_MIN in Table 50. Added RocketIO and PowerPC parameters to Table 1, Table 2, and Table 3. Removed conditions from VIDIFF and VICM in Table 9. Revised Table 13. Added RocketIO DC Input and Output Levels section. Added PowerPC Switching Characteristics section. Added RocketIO Switching Characteristics section. Removed Table 31 from version 1.4. Revised Table 35. Along with changes to Table 43 and Table 50, there are three new requirements to ensure maximum operating frequencies for the DCM. Added parameters to Table 54, Table 55, Table 56, Table 58, Table 59, Table 60, Table 61, Table 62. Revised VIN and VTS in Table 1 and Note 4. Revised typical PCPU specification in Table 3. Revised symbols and values in the Processor tables: Table 16 through Table 22. Revised TDCREF in Table 24. Corrected the CLKOUT_FREQ_FX_HF_MS_MIN in Table 45, the CLKOUT_FREQ_FX_LF_MR_MIN in Table 46, and the "Input Clock Period Jitter" in Table 47. Corrected units in Table 59. Changed VIL and VIH for LVCMOS15 in Table 7. Revised Table 14. Replaced value for VEYE in Table 25. Added Note 4 to Table 50. Added Table 57: Global Clock Setup and Hold for LVCMOS25 Standard, with DCM in Source-Synchronous Mode. Added value for XC4VLX160-FF1513 in Table 60. Added values for -12 speed specifications to most of the tables. Revised the -10 and -11 speeds in most of the switching characteristics tables. Updated to speed specification v1.56. Added VCC_CONFIG note to Table 2. Clarified design information in Table 13. Corrected TPROGRAM in Table 43. Added DRP configuration timing for DCMs to Table 43. Added global clock tree maximum frequency to Table 44. Corrected CLKOUT_FREQ_FX_LF_MS_MIN in Table 45. Added footnotes 3 and 4 to Table 45 and Table 46. Added more data to the TCKSKEW in Table 59. Corrected VOCM in Table 8. Revised Table 11. Added RocketIO MGT Clock DC Input Levels to Table 12. Revised SFI-4.1 performance values in Table 13. Added software tools requirements ISE7.1i SP4, to description above Table 14. Added -11X speed grade to Table 14 and Table 23. Edited Table 15 and Table 16. Edited Table 24. Added note 2 to Table 25, and moved RXOOBVDPP to Table 12. Added conditions to TDJ and TRJ in Table 26. Moved TXOOBVDPP to Table 12. Added RSDS to Table 27. Added note 4 to Table 49. Added Production Stepping section. Table 2: Removed Note 1. Recommended maximum voltage drop for VCCAUX is 10 mV/ms.
02/24/05
1.4
05/19/05
1.5
06/17/05
1.6
06/27/05
1.7
08/06/05
1.8
08/29/05
1.9
09/28/05
1.10
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 52
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Date 02/03/06
Version 1.11
Revisions Revised the speed specification requirements in Switching Characteristics, page 12, with parameter changes in Table 54 and Table 56. Added Note 7 to Table 2. Added to the IRPU and IRPD specifications in Table 3. Changed LVCMOS18 to meet the JEDEC specification in Table 7. Inserted notes into Table 8, Table 9, and Table 10. Corrected note 1 in Table 11. In Table 12, revised Common Mode Input Voltage Range (VICM) typical from 800 mV to 600 mV and added a new Note 1. Also in Table 12, changed Common Mode Voltage specification from 95mV to 950mV. Changed performance numbers in Table 23. Removed the typical specification for TDJ from Table 26. Added note 2 to Table 27. In Table 35, added maximum to TIDELAYCTRLCO_RDY, and a new parameter TIDELAYPAT_JIT. Revised Note 1 in Table 43. Added note 5 to Table 45. Revised notes 3 and 5 in Table 50. Changed the CLKIN_FREQ_PMCD_CLKA_MAX -12 specification in Table 53. Changed the TBUFIO_MAX_FREQ specification in Table 59. Changed the information in the Production Stepping and Current Virtex-4 Production Devices sections. Modified second paragraph in Power-On Power Supply Requirements. Added/Changed numbers for ICCINTMIN, ICCAUXMIN, and ICCOMIN, and added Note 2 (Table 5). Changed the typ value of the DC Parameter, Common Mode Input Voltage Range from 600 MV to 800 MV in Table 12. Added three DC parameters to Table 12, Input Common-Mode Voltage (VICMC), Peak-to-Peak Differential Input Voltage (VIDIFF), and Differential Input Resistance (RIN). Changed the SPI4.2 entry for -11 from 900 Mb/s to 1 Gb/s in Table 13. Added Note 3 to Table 15. Reduced the maximum frequency from 322 MHz to 250 MHz (in Table 25 and Table 26). Added Note 5 to Table 40. Changed VIN and VTS values and added notes to Table 1, page 1. Removed -11X speed grade from Table 14. Updated to speed specification v1.60. Removed -11X speed grade, changed the -12 and -11 speed grade to 6.5 Gb/s, and deleted Note 1 in Table 23, page 16. Deleted first condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Reference Clock total jitter, peak-peak (TGJTT) in Table 24, page 16. Changed the max value for Serial data rate FGTX to 6.5 Gb/s. Deleted first condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Serial data output deterministic jitter (TDJ) and deleted first condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Serial data output random jitter (TRJ), both in Table 26, page 18. Virtex-4 FPGA Electrical Characteristics, page 1: removed paragraph on that introduced the -11x for XC4VFX devices. Table 3, page 3: added new values for ICCAUXRX , ICCAUXTX, ICCCAUXMGT, ITTX , ITRX , and new notes 2 and 3. Table 4, page 4: added new symbols and for values ICCAUXRX, ICCAUXTX, ITTX , ITRX ,IAUMGT and new notes 4 and 5. Table 12, page 11: changed DC parameters and values and added note. Table 14: changed speed designations for the XC4VFX devices. Table 24, page 16 and Table 25, page 17, for most characteristics: changed conditions, speed grade (typ and max) values, and units. Table 26, page 18, for most characteristics: changed conditions, speed grade (typ and max) values, and units. Updated notes. Table 43, page 35: removed the Tcnfig symbol, values, and note 1. Note 2 is now Note 1, and the reference has also been changed. Table 50, page 41: removed Input Signal Requirements. Table 54, page 43, Table 55, page 44, Table 56, page 45, Table 57, page 46, and Table 58, page 47: corrected large speed numbers to N/A. Table 24, page 16: changed value for Reference Clock Rise/Fall Time (TRCLK; TFCLK) from 65 ps Typ to 400 ps Max. Table 35, page 29: changed the speeds specification for the -12, -11, and -10 Speed Grades for TIDELAYRESOLUTION , deleted row for TIDELAYRESOLUTION_ERR and added row for TIDELAYTOTAL_ERR. Table 39, page 31: changed the speeds specification for -12 Speed Grades, Sequential Delay characteristics: TREG , TREGXB, TREGYB, TCKSH, and TREGF5. Table 65, page 51: added stepping information for Virtex-4 FX devices.
03/22/06
1.12
06/01/06
1.13
06/23/06
1.14.1
08/23/06
1.15
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 53
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Date 09/07/06
Version 1.16
Revisions Added 2.5V rows to VIN and VTS (Table 1, page 1). Updated value DVIN from 200 mV to 110 mV in Table 12, page 11. Updated speed grade specifications for XCV4FX devices in Table 14. Updated jitter tolerance and VEYE in Table 25, page 17. Corrected equation for TIDELAYTOTAL_ERR in Table 35, page 29. * * * * SPEED SPECIFICATION version for this data sheet release: v1.62. Table 1: Removed former note 3 on VIN . Table 14: Moved XC4VFX12-11, XC4VFX20-11, XC4VFX60-11, and XC4VFX100-11 devices to Production status. Table 15: Expanded to break out processor clock specifications into Characteristics when APU Not Used and Characteristics when APU Used. Removed specs for CPMFCMCLK, not available. Table 25, Table 26: Updated RX and TX jitter data and notes. Table 39: Modified TREGXB, TREGYB, and TCKSH timing parameters to comply with v1.62 speed specification. SPEED SPECIFICATION version for this data sheet release: v1.62. Table 1: Modified Note (3) referring to 3.3V I/O design guidelines. Added IIN parameters. Table 2: Corrected recommended VTRX range to 0.25V - 2.5V. Added IIN parameters. Table 7: Added LVDCI attributes with LVCMOS. Table 13: Added Note (1) for SDR LVDS Interface requiring AC coupling above 622 MHz. Added DDR2 SDRAM (High-Performance SERDES Design) with reference to XAPP721. Updated all specification values. Pin-to-Pin Performance and Register-to-Register Performance tables (formerly Table 13 and Table 14) deleted. Table 14: XC4VFX12 changed to Production status. Table 15: Added APU-used max characteristics for -12 devices. Table 24: Added values for Spread-Spectrum Clocking and footnote. Table 26: Changed symbol for jitter parameters from TJ, RJ, and DJ to TJ, RJ, and DJ respectively. Table 32: Added Note (1) to refer to Timing Report for non-zero tap values. Made DLY setup/hold parameters relative to C, not CLKDIV. Table 34: Amended Note (1) to refer to Timing Report for non-zero tap values. Table 35: Added Note (1) to refer to XAPP707 for details on IDELAY timing characteristics. Changed TIDELAYRESOLUTION from 74 ps to 75 ps to match Timing Analyzer. Modified formula for TIDELAYTOTAL_ERR to use 75 ps resolution. Table 40: Added CLK-to-DOUT parameters for "with ECC" case. Added CLK-to-CLK parameter. Table 43, Table 44, Table 59: Added configuration parameter values for -12 speed grade. Table 45: Added FMAX for -12 speed grade. Table 45, Table 46, Table 47: Added Note (6) stating that CLKIN values for DLL only also apply to DLL and DFS together. Table 46, Table 47: Replicated Note (5) from Table 45 and applied to all CLKIN with DLL parameters. Table 47, Table 50: Added notes to clarify boundary-frequency cases. Table 48: Modified Note (1) to point to the architecture wizard for CLKFX output jitter. Added Note (2) to indicate that PMCD outputs introduce no jitter.
10/06/06
1.17
* * 12/11/06 2.0 * * * * *
* * * * * * * *
* * * * * * *
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 54
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Date 12/11/06 (Cont'd)
Version 2.0 (Cont'd) * * * * * * * * * * * * * *
Revisions Table 50: Removed T_LOCK_FX_MIN parameter. Added DCM_RESET. Table 53: Added Note (1), no minimum frequency for PMCD. Table 64: Added Note (1) to refer to LX and SX Errata for capability improvements. SPEED SPECIFICATION version for this data sheet release: v1.64. Table 4: Added Note (6) regarding max quiescent supply current. Table 5: Filled in missing power-on current values for FX devices. Table 24: Added new parameter FGREFCLK. Added Min value for Spread Spectrum Clocking frequency. Corrected "Conditions". Table 26: Revised Notes (2) and (3). Table 37, Table 38: Added column/values for XC4VFX -12. Table 39: Added columns/values for XC4VFX -11 and -12. Corrected XC4VLX/SX -11 and -12 values for TREGXB, TREGYB, and TCKSH. Table 43: Restored parameter TCONFIG and footnote (1) from earlier revision. Added new parameter TSMCO (SelectMAP Readback Clock-to-Out). Table 50: Restored DCM_RESET Minimum and DCM_INPUT_CLOCK_STOP parameters from earlier revision. Added Notes (4) through (7) to these parameters. Table 60: Removed FF1760 package. Not supported. Table 63: Added FX devices and JTAG IDs. SPEED SPECIFICATION version for this data sheet release: v1.65. Table 14: Promoted -12 speed grade devices of XC4VFX12, XC4VFX20, and XC4VFX60 to Production status. Table 37: Removed parameter TISCCK_REV. Not meaningful because pin should always be connected to GND. Table 43: Added parameter FMAX_SELECTMAP. for maximum Slave SelectMAP mode external configuration clock frequency. Table 63: Filled in Step 1 values for XC4VFX20, XC4VFX60, and XC4VFX100. Table 65: Added Step 1 data. SPEED SPECIFICATION version for this data sheet release: v1.65. Table 3: Added MAX value for IBATT . Table 25: Added unit (ns) to RXSIGDET. Table 27: Added Note (3) specifying range of DCI reference resistors and referring to UG070. Added section Ethernet MAC Switching Characteristics, page 22, and replaced Table 29. Added section I/O Standard Adjustment Measurement Methodology, page 23, including Table 30, Table 31, and Figure 4. Table 43: Added parameter FMAX_ICAP . Added word "Data" to description of SelectMAP Setup/Hold. Table 64: Added to Capability Improvements, for Step 1 that the DFS macro is no longer needed. SPEED SPECIFICATION version for this data sheet release: v1.67. Table 14: Promoted all speed grades for XC4VFX40 devices, and -12 speed grade for XC4VFX100 devices, to Production status. Table 63: Filled in Step 1 value for XC4VFX40. Table 65: Added Note 1.
03/27/07
2.1
06/08/07
2.2
* * * * * *
08/10/07
2.3
* * * * * * * *
09/10/07
2.4
* * * *
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 55
R
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Date 09/28/07
Version 3.0 * * * * * *
Revisions SPEED SPECIFICATION version for this data sheet release: v1.67. Promoted data sheet to Production status. Table 14: Moved XC4VFX140, all speed grades, from Advance to Production status. Table 59: Added/updated all Global Clock Tree Skew values. Qualified Note (2) by adding "vertical". Table 60: Added Package Skew values for XC4VFX40, XC4VFX100, and XC4VFX140. Table 63: Added JTAG ID code for XC4VFX140. SPEED SPECIFICATION version for this data sheet release: v1.68. Added new copyright notice and legal disclaimer section. Table 13: Removed table note references to XAPP700, XAPP704, and XAPP705 (obsolete). Renumbered table notes. Table 15: Added new Note 1, renumbered subsequent table notes. Table 30: Removed table rows for LVPECL_33, LVDS_33, and LVDSEXT_33. Table 30, Table 31: Corrected "electron-coupled" to "emitter-coupled". Table 31: For LVDS Extended Mode 2.5V, corrected I/O Standard Attribute to LVDSEXT_25. Table 37: Added Note 4 specifying FTOG for -11 FX devices as 1181 MHz. Table 43: Added parameter FMAX_READBACK . Table 58: Corrected TPSFD for XC4VFX100 devices to 1.99 ns. Section Production Stepping, page 50: Advised that current stepping level is reported by the ISE tool in the PAR report. SPEED SPECIFICATION version for this data sheet release: v1.68. Table 28, page 22: Re-inserted table. Table 43, page 35: Updated Symbol names for the DRP entries. Table 63, page 50: Revised code for XC4VFX40 package to 0.
12/11/07
3.1
* * * * * * * * * * *
04/10/08
3.2
* * * *
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
DS302 (v3.2) April 10, 2008 Product Specification
www.xilinx.com 56

▲Up To Search▲

Price & Availability of XC4VLX15

	To Download XC4VLX15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .